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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 1d3409ba822566404d008bc08cdc60c11a44da62 / . / openlane / cntr_example / runs / cntr_example / reports / synthesis / 2-syn_sta.min.rpt
blob: 4e89e1b8eed5dce67153675ad3e5ae06a5037646 [file] [log] [blame]
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.83 1.07 1.07 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[14] (net)
0.83 0.00 1.07 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.28 0.30 1.37 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _052_ (net)
0.28 0.00 1.37 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.12 0.09 1.46 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 _018_ (net)
0.12 0.00 1.46 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.46 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.09 0.34 library hold time
0.34 data required time
-----------------------------------------------------------------------------
0.34 data required time
-1.46 data arrival time
-----------------------------------------------------------------------------
1.12 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.83 1.07 1.07 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[18] (net)
0.83 0.00 1.07 v _064_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.28 0.30 1.37 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _026_ (net)
0.28 0.00 1.37 ^ _068_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.12 0.09 1.46 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 _002_ (net)
0.12 0.00 1.46 v _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.46 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.09 0.34 library hold time
0.34 data required time
-----------------------------------------------------------------------------
0.34 data required time
-1.46 data arrival time
-----------------------------------------------------------------------------
1.12 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.83 1.07 1.07 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[2] (net)
0.83 0.00 1.07 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.28 0.30 1.37 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _034_ (net)
0.28 0.00 1.37 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.12 0.09 1.46 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 _006_ (net)
0.12 0.00 1.46 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.46 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.09 0.34 library hold time
0.34 data required time
-----------------------------------------------------------------------------
0.34 data required time
-1.46 data arrival time
-----------------------------------------------------------------------------
1.12 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.83 1.07 1.07 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[6] (net)
0.83 0.00 1.07 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.28 0.30 1.37 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _040_ (net)
0.28 0.00 1.37 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.12 0.09 1.46 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 _010_ (net)
0.12 0.00 1.46 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.46 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.09 0.34 library hold time
0.34 data required time
-----------------------------------------------------------------------------
0.34 data required time
-1.46 data arrival time
-----------------------------------------------------------------------------
1.12 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.83 1.07 1.07 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[10] (net)
0.83 0.00 1.07 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.28 0.30 1.37 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _046_ (net)
0.28 0.00 1.37 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.12 0.09 1.46 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 _014_ (net)
0.12 0.00 1.46 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.46 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.09 0.34 library hold time
0.34 data required time
-----------------------------------------------------------------------------
0.34 data required time
-1.46 data arrival time
-----------------------------------------------------------------------------
1.12 slack (MET)