openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.max.rpt

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  1.56    1.62    1.62 ^ _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     5    0.09                           io_out[13] (net)
                  1.56    0.00    1.62 ^ io_out[13] (out)
                                  1.62   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -1.62   data arrival time
-----------------------------------------------------------------------------
                                 50.13   slack (MET)


Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  1.56    1.62    1.62 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     5    0.09                           io_out[17] (net)
                  1.56    0.00    1.62 ^ io_out[17] (out)
                                  1.62   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -1.62   data arrival time
-----------------------------------------------------------------------------
                                 50.13   slack (MET)


Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  1.56    1.62    1.62 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     5    0.09                           io_out[1] (net)
                  1.56    0.00    1.62 ^ io_out[1] (out)
                                  1.62   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -1.62   data arrival time
-----------------------------------------------------------------------------
                                 50.13   slack (MET)


Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  1.56    1.62    1.62 ^ _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     5    0.09                           io_out[5] (net)
                  1.56    0.00    1.62 ^ io_out[5] (out)
                                  1.62   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -1.62   data arrival time
-----------------------------------------------------------------------------
                                 50.13   slack (MET)


Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  1.56    1.62    1.62 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     5    0.09                           io_out[9] (net)
                  1.56    0.00    1.62 ^ io_out[9] (out)
                                  1.62   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -1.62   data arrival time
-----------------------------------------------------------------------------
                                 50.13   slack (MET)