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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 1d3409ba822566404d008bc08cdc60c11a44da62 / . / openlane / cntr_example / runs / cntr_example / reports / signoff / 22-rcx_sta.min.rpt
blob: 275f921ad18eb74778e4ab026a31b45565750488 [file] [log] [blame]
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.87 2.18 2.72 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
2.88 0.06 2.78 ^ fanout23/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.71 0.53 3.31 ^ fanout23/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net23 (net)
0.71 0.00 3.31 ^ _095_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.35 0.90 4.20 v _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.19 _013_ (net)
1.36 0.07 4.27 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.27 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.27 0.53 library hold time
0.53 data required time
-----------------------------------------------------------------------------
0.53 data required time
-4.27 data arrival time
-----------------------------------------------------------------------------
3.74 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.80 1.61 2.15 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
1.81 0.06 2.21 v _110_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.38 0.66 2.88 ^ _110_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _055_ (net)
0.38 0.00 2.88 ^ _111_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.93 1.22 4.10 v _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
1.93 0.04 4.14 v _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.14 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.41 0.39 library hold time
0.39 data required time
-----------------------------------------------------------------------------
0.39 data required time
-4.14 data arrival time
-----------------------------------------------------------------------------
3.75 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.07 1.75 2.30 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
2.08 0.08 2.38 v _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.50 0.96 3.34 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _020_ (net)
0.50 0.00 3.34 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.90 1.46 4.81 ^ _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _001_ (net)
1.91 0.05 4.86 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.86 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.03 0.82 clock reconvergence pessimism
0.14 0.96 library hold time
0.96 data required time
-----------------------------------------------------------------------------
0.96 data required time
-4.86 data arrival time
-----------------------------------------------------------------------------
3.90 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.20 1.82 2.36 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
2.21 0.08 2.45 v fanout22/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.46 0.96 3.40 v fanout22/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net22 (net)
0.46 0.00 3.40 v _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.38 0.34 3.74 ^ _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _051_ (net)
0.38 0.00 3.74 ^ _105_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.17 0.76 4.50 v _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _017_ (net)
1.18 0.05 4.55 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.55 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.22 0.57 library hold time
0.57 data required time
-----------------------------------------------------------------------------
0.57 data required time
-4.55 data arrival time
-----------------------------------------------------------------------------
3.98 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.95 1.68 2.23 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
1.96 0.07 2.30 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.76 1.10 3.41 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net25 (net)
0.76 0.00 3.41 v _074_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.38 0.38 3.79 ^ _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _033_ (net)
0.38 0.00 3.79 ^ _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.22 0.79 4.58 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.17 _005_ (net)
1.23 0.06 4.63 v _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.63 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.23 0.57 library hold time
0.57 data required time
-----------------------------------------------------------------------------
0.57 data required time
-4.63 data arrival time
-----------------------------------------------------------------------------
4.06 slack (MET)