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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 1d3409ba822566404d008bc08cdc60c11a44da62 / . / openlane / cntr_example / runs / cntr_example / reports / signoff / 22-rcx_sta.max.rpt
blob: 977b65ab05910050df379f05c08500e450e78551 [file] [log] [blame]
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.40 0.00 16.63 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
10.13 6.14 22.77 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
10.13 0.15 22.92 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
22.92 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.70 65.99 library setup time
65.99 data required time
-----------------------------------------------------------------------------
65.99 data required time
-22.92 data arrival time
-----------------------------------------------------------------------------
43.07 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.34 0.00 16.59 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.73 4.70 21.29 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.26 _004_ (net)
7.73 0.11 21.40 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.40 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.43 65.72 library setup time
65.72 data required time
-----------------------------------------------------------------------------
65.72 data required time
-21.40 data arrival time
-----------------------------------------------------------------------------
44.32 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.56 0.56 16.29 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.56 0.00 16.29 ^ _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.30 0.16 16.45 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _042_ (net)
0.30 0.00 16.45 v _089_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.76 4.71 21.17 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.27 _010_ (net)
7.77 0.11 21.28 ^ _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.28 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.43 65.73 library setup time
65.73 data required time
-----------------------------------------------------------------------------
65.73 data required time
-21.28 data arrival time
-----------------------------------------------------------------------------
44.45 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.40 0.00 16.63 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.31 4.47 21.10 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _011_ (net)
7.32 0.10 21.20 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.20 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.38 65.67 library setup time
65.67 data required time
-----------------------------------------------------------------------------
65.67 data required time
-21.20 data arrival time
-----------------------------------------------------------------------------
44.47 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.34 0.00 16.59 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.20 4.38 20.97 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _012_ (net)
7.20 0.10 21.08 ^ _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.08 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.37 65.67 library setup time
65.67 data required time
-----------------------------------------------------------------------------
65.67 data required time
-21.08 data arrival time
-----------------------------------------------------------------------------
44.59 slack (MET)