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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 1d3409ba822566404d008bc08cdc60c11a44da62 / . / openlane / cntr_example / runs / cntr_example / reports / routing / 16-grt_sta.min.rpt
blob: 152bae18141180e15364bffacb201437393dfacc [file] [log] [blame]
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.52 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.04 clknet_1_1__leaf_wb_clk_i (net)
0.11 0.00 0.52 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.36 0.79 1.31 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.03 net3 (net)
0.36 0.01 1.32 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.27 0.22 1.55 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _046_ (net)
0.27 0.00 1.55 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.30 0.24 1.79 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.02 _014_ (net)
0.30 0.00 1.79 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.79 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.04 clknet_1_1__leaf_wb_clk_i (net)
0.11 0.00 0.58 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.83 clock uncertainty
-0.06 0.77 clock reconvergence pessimism
0.03 0.80 library hold time
0.80 data required time
-----------------------------------------------------------------------------
0.80 data required time
-1.79 data arrival time
-----------------------------------------------------------------------------
0.99 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.52 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.04 clknet_1_1__leaf_wb_clk_i (net)
0.11 0.00 0.52 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.37 0.79 1.32 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.03 net18 (net)
0.37 0.01 1.33 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.27 0.22 1.55 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _040_ (net)
0.27 0.00 1.55 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.30 0.24 1.79 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.02 _010_ (net)
0.30 0.00 1.80 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.80 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.04 clknet_1_1__leaf_wb_clk_i (net)
0.11 0.00 0.58 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.83 clock uncertainty
-0.06 0.77 clock reconvergence pessimism
0.03 0.80 library hold time
0.80 data required time
-----------------------------------------------------------------------------
0.80 data required time
-1.80 data arrival time
-----------------------------------------------------------------------------
0.99 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.52 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.04 clknet_1_1__leaf_wb_clk_i (net)
0.11 0.00 0.52 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.38 0.80 1.33 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.04 net14 (net)
0.38 0.01 1.34 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.28 0.23 1.57 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _034_ (net)
0.28 0.00 1.57 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.30 0.24 1.81 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.02 _006_ (net)
0.30 0.00 1.81 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.81 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.04 clknet_1_1__leaf_wb_clk_i (net)
0.11 0.00 0.58 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.83 clock uncertainty
-0.06 0.77 clock reconvergence pessimism
0.03 0.80 library hold time
0.80 data required time
-----------------------------------------------------------------------------
0.80 data required time
-1.81 data arrival time
-----------------------------------------------------------------------------
1.01 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.10 0.23 0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.10 0.00 0.52 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.38 0.80 1.32 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.04 net7 (net)
0.38 0.01 1.33 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.28 0.23 1.56 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _052_ (net)
0.28 0.00 1.56 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.31 0.25 1.81 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.02 _018_ (net)
0.31 0.01 1.82 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.82 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.10 0.00 0.58 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.83 clock uncertainty
-0.05 0.77 clock reconvergence pessimism
0.03 0.80 library hold time
0.80 data required time
-----------------------------------------------------------------------------
0.80 data required time
-1.82 data arrival time
-----------------------------------------------------------------------------
1.02 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.10 0.23 0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.10 0.00 0.52 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.35 0.78 1.30 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.03 net4 (net)
0.35 0.01 1.31 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.28 0.24 1.55 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.00 _049_ (net)
0.28 0.00 1.55 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.31 0.26 1.81 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.02 _015_ (net)
0.31 0.00 1.82 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.82 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.10 0.00 0.58 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.83 clock uncertainty
-0.05 0.77 clock reconvergence pessimism
0.03 0.80 library hold time
0.80 data required time
-----------------------------------------------------------------------------
0.80 data required time
-1.82 data arrival time
-----------------------------------------------------------------------------
1.02 slack (MET)