| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.33 0.78 0.78 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net3 (net) |
| 0.33 0.01 0.79 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.26 0.22 1.00 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _046_ (net) |
| 0.26 0.00 1.00 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.23 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _014_ (net) |
| 0.29 0.00 1.23 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.23 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.23 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.94 slack (MET) |
| |
| |
| Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.34 0.78 0.78 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net18 (net) |
| 0.34 0.01 0.79 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.01 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _040_ (net) |
| 0.27 0.00 1.01 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.24 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _010_ (net) |
| 0.29 0.00 1.24 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.24 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.24 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.95 slack (MET) |
| |
| |
| Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.35 0.79 0.79 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net14 (net) |
| 0.35 0.01 0.80 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.03 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _034_ (net) |
| 0.27 0.00 1.03 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.25 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _006_ (net) |
| 0.29 0.00 1.26 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.26 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.26 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.97 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.34 0.79 0.79 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net7 (net) |
| 0.34 0.01 0.80 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.02 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _052_ (net) |
| 0.27 0.00 1.02 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.26 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _018_ (net) |
| 0.30 0.00 1.26 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.26 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.26 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.97 slack (MET) |
| |
| |
| Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.32 0.78 0.78 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2 0.03 net4 (net) |
| 0.33 0.01 0.79 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.28 0.23 1.02 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.00 _049_ (net) |
| 0.28 0.00 1.02 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.25 1.27 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _015_ (net) |
| 0.29 0.00 1.27 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.27 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.27 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.98 slack (MET) |
| |
| |