openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.max.rpt

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.11    0.04   13.04 ^ wb_rst_i (in)
     1    0.00                           wb_rst_i (net)
                  0.11    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
                  0.28    0.36   13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
     2    0.03                           net1 (net)
                  0.28    0.01   13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.35    0.38   13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _021_ (net)
                  0.35    0.00   13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
                  0.33    0.29   14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
     4    0.02                           _022_ (net)
                  0.33    0.00   14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.33    0.41   14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _030_ (net)
                  0.33    0.00   14.49 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.61    0.46   14.95 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _007_ (net)
                  0.61    0.00   14.95 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 14.95   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.25   64.50   library setup time
                                 64.50   data required time
-----------------------------------------------------------------------------
                                 64.50   data required time
                                -14.95   data arrival time
-----------------------------------------------------------------------------
                                 49.55   slack (MET)


Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.11    0.04   13.04 ^ wb_rst_i (in)
     1    0.00                           wb_rst_i (net)
                  0.11    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
                  0.28    0.36   13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
     2    0.03                           net1 (net)
                  0.28    0.01   13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.35    0.38   13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _021_ (net)
                  0.35    0.00   13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
                  0.33    0.29   14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
     4    0.02                           _022_ (net)
                  0.33    0.00   14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.33    0.41   14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _030_ (net)
                  0.33    0.00   14.49 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.61    0.46   14.95 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _011_ (net)
                  0.61    0.00   14.95 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 14.95   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.25   64.50   library setup time
                                 64.50   data required time
-----------------------------------------------------------------------------
                                 64.50   data required time
                                -14.95   data arrival time
-----------------------------------------------------------------------------
                                 49.55   slack (MET)


Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.11    0.04   13.04 ^ wb_rst_i (in)
     1    0.00                           wb_rst_i (net)
                  0.11    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
                  0.28    0.36   13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
     2    0.03                           net1 (net)
                  0.28    0.01   13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.35    0.38   13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _021_ (net)
                  0.35    0.00   13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
                  0.33    0.29   14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
     4    0.02                           _022_ (net)
                  0.33    0.00   14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.33    0.41   14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _030_ (net)
                  0.33    0.00   14.49 v _071_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.61    0.45   14.94 ^ _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _003_ (net)
                  0.61    0.00   14.95 ^ _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 14.95   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.25   64.50   library setup time
                                 64.50   data required time
-----------------------------------------------------------------------------
                                 64.50   data required time
                                -14.95   data arrival time
-----------------------------------------------------------------------------
                                 49.55   slack (MET)


Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.11    0.04   13.04 ^ wb_rst_i (in)
     1    0.00                           wb_rst_i (net)
                  0.11    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
                  0.28    0.36   13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
     2    0.03                           net1 (net)
                  0.28    0.01   13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.35    0.38   13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _021_ (net)
                  0.35    0.00   13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
                  0.33    0.29   14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
     4    0.02                           _022_ (net)
                  0.33    0.00   14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.33    0.41   14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _030_ (net)
                  0.33    0.00   14.49 v _103_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.61    0.45   14.94 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _016_ (net)
                  0.61    0.00   14.95 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 14.95   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.25   64.50   library setup time
                                 64.50   data required time
-----------------------------------------------------------------------------
                                 64.50   data required time
                                -14.95   data arrival time
-----------------------------------------------------------------------------
                                 49.55   slack (MET)


Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.11    0.04   13.04 ^ wb_rst_i (in)
     1    0.00                           wb_rst_i (net)
                  0.11    0.00   13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
                  0.28    0.36   13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
     2    0.03                           net1 (net)
                  0.28    0.01   13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.35    0.38   13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _021_ (net)
                  0.35    0.00   13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
                  0.33    0.29   14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
     4    0.02                           _022_ (net)
                  0.33    0.00   14.08 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
                  0.31    0.40   14.48 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
     4    0.02                           _023_ (net)
                  0.31    0.00   14.48 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
                  0.62    0.46   14.94 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
     1    0.02                           _004_ (net)
                  0.62    0.00   14.94 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 14.94   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.25   64.50   library setup time
                                 64.50   data required time
-----------------------------------------------------------------------------
                                 64.50   data required time
                                -14.94   data arrival time
-----------------------------------------------------------------------------
                                 49.56   slack (MET)