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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 1d3409ba822566404d008bc08cdc60c11a44da62 / . / openlane / cntr_example / runs / cntr_example / reports / placement / 7-gpl_sta.min.rpt
blob: 8d3fbc9523a9e48d5cad4ac2d6c305f76d09ba39 [file] [log] [blame]
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.95 1.13 1.13 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[10] (net)
0.95 0.04 1.17 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.29 0.32 1.49 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _046_ (net)
0.29 0.00 1.49 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.29 0.23 1.72 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.02 _014_ (net)
0.29 0.00 1.72 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.72 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.04 0.29 library hold time
0.29 data required time
-----------------------------------------------------------------------------
0.29 data required time
-1.72 data arrival time
-----------------------------------------------------------------------------
1.43 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.96 1.13 1.13 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[6] (net)
0.96 0.04 1.17 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.29 0.32 1.49 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _040_ (net)
0.29 0.00 1.49 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.29 0.23 1.72 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.02 _010_ (net)
0.29 0.00 1.73 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.73 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.04 0.29 library hold time
0.29 data required time
-----------------------------------------------------------------------------
0.29 data required time
-1.73 data arrival time
-----------------------------------------------------------------------------
1.44 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.97 1.14 1.14 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[2] (net)
0.98 0.04 1.18 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.29 0.32 1.50 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _034_ (net)
0.29 0.00 1.50 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.29 0.23 1.73 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.02 _006_ (net)
0.29 0.00 1.74 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.74 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.04 0.29 library hold time
0.29 data required time
-----------------------------------------------------------------------------
0.29 data required time
-1.74 data arrival time
-----------------------------------------------------------------------------
1.45 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.96 1.14 1.14 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[14] (net)
0.97 0.04 1.18 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.30 0.33 1.50 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _052_ (net)
0.30 0.00 1.50 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.30 0.24 1.74 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.02 _018_ (net)
0.30 0.00 1.75 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.75 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.04 0.29 library hold time
0.29 data required time
-----------------------------------------------------------------------------
0.29 data required time
-1.75 data arrival time
-----------------------------------------------------------------------------
1.46 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.98 1.14 1.14 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.08 io_out[18] (net)
0.99 0.04 1.19 v _064_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.29 0.33 1.51 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _026_ (net)
0.29 0.00 1.51 ^ _068_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.30 0.24 1.75 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.02 _002_ (net)
0.30 0.00 1.75 v _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.75 data arrival time
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
0.25 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.04 0.29 library hold time
0.29 data required time
-----------------------------------------------------------------------------
0.29 data required time
-1.75 data arrival time
-----------------------------------------------------------------------------
1.46 slack (MET)