| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.22 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.10 0.00 0.51 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.33 0.77 1.28 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net3 (net) |
| 0.33 0.01 1.29 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.26 0.22 1.51 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _046_ (net) |
| 0.26 0.00 1.51 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.73 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _014_ (net) |
| 0.29 0.00 1.74 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.74 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.10 0.00 0.57 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.82 clock uncertainty |
| -0.05 0.76 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.74 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.94 slack (MET) |
| |
| |
| Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.22 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.10 0.00 0.51 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.34 0.77 1.29 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net18 (net) |
| 0.34 0.01 1.30 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.51 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _040_ (net) |
| 0.27 0.00 1.51 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.74 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _010_ (net) |
| 0.29 0.00 1.75 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.75 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.10 0.00 0.57 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.82 clock uncertainty |
| -0.05 0.76 clock reconvergence pessimism |
| 0.03 0.79 library hold time |
| 0.79 data required time |
| ----------------------------------------------------------------------------- |
| 0.79 data required time |
| -1.75 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.95 slack (MET) |
| |
| |
| Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.22 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.10 0.00 0.51 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.35 0.78 1.30 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net14 (net) |
| 0.35 0.01 1.31 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.53 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _034_ (net) |
| 0.27 0.00 1.53 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.76 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _006_ (net) |
| 0.29 0.00 1.76 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.76 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.10 0.00 0.57 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.82 clock uncertainty |
| -0.05 0.76 clock reconvergence pessimism |
| 0.03 0.79 library hold time |
| 0.79 data required time |
| ----------------------------------------------------------------------------- |
| 0.79 data required time |
| -1.76 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.97 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.23 0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.52 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.34 0.78 1.30 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net7 (net) |
| 0.35 0.01 1.31 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.53 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _052_ (net) |
| 0.27 0.00 1.53 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.77 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _018_ (net) |
| 0.30 0.00 1.77 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.77 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.57 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.82 clock uncertainty |
| -0.05 0.77 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.77 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.98 slack (MET) |
| |
| |
| Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.23 0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.52 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.32 0.77 1.28 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2 0.03 net4 (net) |
| 0.33 0.01 1.29 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.28 0.23 1.53 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.00 _049_ (net) |
| 0.28 0.00 1.53 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.25 1.78 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _015_ (net) |
| 0.29 0.00 1.78 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.78 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.57 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.82 clock uncertainty |
| -0.05 0.77 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.78 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.98 slack (MET) |
| |
| |