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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 1d3409ba822566404d008bc08cdc60c11a44da62 / . / openlane / cntr_example / runs / cntr_example / logs / synthesis / 1-synthesis.log
blob: 727c9ee91690a84581a3eb9bcd6b2c1fbddb2e25 [file] [log] [blame]
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Verilog-2005 frontend: /home/htf6ry/gf180-demo-fiveguys/caravel/verilog/rtl/defines.v
Parsing SystemVerilog input from `/home/htf6ry/gf180-demo-fiveguys/caravel/verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v
Parsing SystemVerilog input from `/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v' to AST representation.
Generating RTLIL representation for module `\cntr_example'.
Generating RTLIL representation for module `\cntr_1'.
Generating RTLIL representation for module `\cntr_2'.
Generating RTLIL representation for module `\cntr_3'.
Generating RTLIL representation for module `\cntr_4'.
Generating RTLIL representation for module `\cntr_5'.
Successfully finished Verilog frontend.
3. Generating Graphviz representation of design.
Writing dot description to `/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/synthesis/hierarchy.dot'.
Dumping module cntr_example to page 1.
Warning: WIDTHLABEL \io_out [19:16] 4
Warning: WIDTHLABEL \io_out [15:12] 4
Warning: WIDTHLABEL \io_out [11:8] 4
Warning: WIDTHLABEL \io_out [7:4] 4
Warning: WIDTHLABEL \io_out [3:0] 4
4. Executing HIERARCHY pass (managing design hierarchy).
4.1. Analyzing design hierarchy..
Top module: \cntr_example
Used module: \cntr_5
Used module: \cntr_4
Used module: \cntr_3
Used module: \cntr_2
Used module: \cntr_1
Parameter \BITS = 20
4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_5'.
Parameter \BITS = 20
Generating RTLIL representation for module `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100'.
Parameter \BITS = 20
4.3. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_4'.
Parameter \BITS = 20
Generating RTLIL representation for module `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100'.
Parameter \BITS = 20
4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_3'.
Parameter \BITS = 20
Generating RTLIL representation for module `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100'.
Parameter \BITS = 20
4.5. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_2'.
Parameter \BITS = 20
Generating RTLIL representation for module `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100'.
Parameter \BITS = 20
4.6. Executing AST frontend in derive mode using pre-parsed AST for module `\cntr_1'.
Parameter \BITS = 20
Generating RTLIL representation for module `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100'.
4.7. Analyzing design hierarchy..
Top module: \cntr_example
Used module: $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
4.8. Analyzing design hierarchy..
Top module: \cntr_example
Used module: $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
Removing unused module `\cntr_5'.
Removing unused module `\cntr_4'.
Removing unused module `\cntr_3'.
Removing unused module `\cntr_2'.
Removing unused module `\cntr_1'.
Removed 5 unused modules.
Warning: Resizing cell port cntr_example.cntr_5.out5 from 4 bits to 20 bits.
Warning: Resizing cell port cntr_example.cntr_4.out4 from 4 bits to 20 bits.
Warning: Resizing cell port cntr_example.cntr_3.out3 from 4 bits to 20 bits.
Warning: Resizing cell port cntr_example.cntr_2.out2 from 4 bits to 20 bits.
Warning: Resizing cell port cntr_example.cntr_1.out1 from 4 bits to 20 bits.
WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v
5. Executing SYNTH pass.
5.1. Executing HIERARCHY pass (managing design hierarchy).
5.1.1. Analyzing design hierarchy..
Top module: \cntr_example
Used module: $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
5.1.2. Analyzing design hierarchy..
Top module: \cntr_example
Used module: $paramod\cntr_5\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_4\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_3\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_2\BITS=s32'00000000000000000000000000010100
Used module: $paramod\cntr_1\BITS=s32'00000000000000000000000000010100
Removed 0 unused modules.
5.2. Executing PROC pass (convert processes to netlists).
5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28 in module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25 in module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22 in module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19 in module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16 in module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
Removed a total of 0 dead cases.
5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 5 redundant assignments.
Promoted 0 assignments to connections.
5.2.4. Executing PROC_INIT pass (extract init attributes).
5.2.5. Executing PROC_ARST pass (detect async resets in processes).
5.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~5 debug messages>
5.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
1/1: $0\out1[19:0]
Creating decoders for process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
1/1: $0\out2[19:0]
Creating decoders for process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
1/1: $0\out3[19:0]
Creating decoders for process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
1/1: $0\out4[19:0]
Creating decoders for process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
1/1: $0\out5[19:0]
5.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
5.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.\out1' using process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
created $dff cell `$procdff$51' with positive edge clock.
Creating register for signal `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.\out2' using process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
created $dff cell `$procdff$52' with positive edge clock.
Creating register for signal `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.\out3' using process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
created $dff cell `$procdff$53' with positive edge clock.
Creating register for signal `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.\out4' using process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
created $dff cell `$procdff$54' with positive edge clock.
Creating register for signal `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.\out5' using process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
created $dff cell `$procdff$55' with positive edge clock.
5.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
5.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
Removing empty process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
Found and cleaned up 1 empty switch in `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
Removing empty process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
Found and cleaned up 1 empty switch in `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
Removing empty process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
Found and cleaned up 1 empty switch in `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
Removing empty process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
Found and cleaned up 1 empty switch in `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
Removing empty process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
Cleaned up 5 empty switches.
5.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
<suppressed ~1 debug messages>
Optimizing module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
<suppressed ~1 debug messages>
Optimizing module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
<suppressed ~1 debug messages>
Optimizing module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
<suppressed ~1 debug messages>
Optimizing module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
<suppressed ~1 debug messages>
Optimizing module cntr_example.
5.3. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
Deleting now unused module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
Deleting now unused module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
Deleting now unused module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
Deleting now unused module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
<suppressed ~5 debug messages>
5.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
Removed 5 unused cells and 20 unused wires.
<suppressed ~6 debug messages>
5.6. Executing CHECK pass (checking for obvious problems).
Checking module cntr_example...
Warning: Wire cntr_example.\io_out [37] is used but has no driver.
Warning: Wire cntr_example.\io_out [36] is used but has no driver.
Warning: Wire cntr_example.\io_out [35] is used but has no driver.
Warning: Wire cntr_example.\io_out [34] is used but has no driver.
Warning: Wire cntr_example.\io_out [33] is used but has no driver.
Warning: Wire cntr_example.\io_out [32] is used but has no driver.
Warning: Wire cntr_example.\io_out [31] is used but has no driver.
Warning: Wire cntr_example.\io_out [30] is used but has no driver.
Warning: Wire cntr_example.\io_out [29] is used but has no driver.
Warning: Wire cntr_example.\io_out [28] is used but has no driver.
Warning: Wire cntr_example.\io_out [27] is used but has no driver.
Warning: Wire cntr_example.\io_out [26] is used but has no driver.
Warning: Wire cntr_example.\io_out [25] is used but has no driver.
Warning: Wire cntr_example.\io_out [24] is used but has no driver.
Warning: Wire cntr_example.\io_out [23] is used but has no driver.
Warning: Wire cntr_example.\io_out [22] is used but has no driver.
Warning: Wire cntr_example.\io_out [21] is used but has no driver.
Warning: Wire cntr_example.\io_out [20] is used but has no driver.
Found and reported 18 problems.
5.7. Executing OPT pass (performing simple optimizations).
5.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cntr_example..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~5 debug messages>
5.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \cntr_example.
Performed a total of 0 changes.
5.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.7.6. Executing OPT_DFF pass (perform DFF optimizations).
5.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.7.9. Finished OPT passes. (There is nothing left to do.)
5.8. Executing FSM pass (extract and optimize FSM).
5.8.1. Executing FSM_DETECT pass (finding FSMs in design).
5.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
5.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
5.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
5.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
5.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
5.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
5.9. Executing OPT pass (performing simple optimizations).
5.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cntr_example..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~5 debug messages>
5.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \cntr_example.
Performed a total of 0 changes.
5.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\cntr_5.$procdff$55 ($dff) from module cntr_example (D = $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y [19:0], Q = \cntr_5.out5, rval = 20'00000000000000000000).
Adding SRST signal on $flatten\cntr_4.$procdff$54 ($dff) from module cntr_example (D = $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y [19:0], Q = \cntr_4.out4, rval = 20'00000000000000000000).
Adding SRST signal on $flatten\cntr_3.$procdff$53 ($dff) from module cntr_example (D = $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y [19:0], Q = \cntr_3.out3, rval = 20'00000000000000000000).
Adding SRST signal on $flatten\cntr_2.$procdff$52 ($dff) from module cntr_example (D = $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y [19:0], Q = \cntr_2.out2, rval = 20'00000000000000000000).
Adding SRST signal on $flatten\cntr_1.$procdff$51 ($dff) from module cntr_example (D = $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y [19:0], Q = \cntr_1.out1, rval = 20'00000000000000000000).
5.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
Removed 5 unused cells and 5 unused wires.
<suppressed ~6 debug messages>
5.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.9.9. Rerunning OPT passes. (Maybe there is more to do..)
5.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cntr_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
5.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \cntr_example.
Performed a total of 0 changes.
5.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.9.13. Executing OPT_DFF pass (perform DFF optimizations).
5.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.9.16. Finished OPT passes. (There is nothing left to do.)
5.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y.
Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y.
Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y.
Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y.
Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y.
5.11. Executing PEEPOPT pass (run peephole optimizers).
5.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
Removed 0 unused cells and 5 unused wires.
<suppressed ~1 debug messages>
5.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module cntr_example:
creating $macc model for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
creating $macc model for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
creating $macc model for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
creating $macc model for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
creating $macc model for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
creating $alu model for $macc $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18.
creating $alu model for $macc $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21.
creating $alu model for $macc $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24.
creating $alu model for $macc $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27.
creating $alu model for $macc $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30.
creating $alu cell for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30: $auto$alumacc.cc:485:replace_alu$66
creating $alu cell for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27: $auto$alumacc.cc:485:replace_alu$69
creating $alu cell for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24: $auto$alumacc.cc:485:replace_alu$72
creating $alu cell for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21: $auto$alumacc.cc:485:replace_alu$75
creating $alu cell for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18: $auto$alumacc.cc:485:replace_alu$78
created 5 $alu and 0 $macc cells.
5.14. Executing SHARE pass (SAT-based resource sharing).
5.15. Executing OPT pass (performing simple optimizations).
5.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cntr_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
5.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \cntr_example.
Performed a total of 0 changes.
5.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.15.6. Executing OPT_DFF pass (perform DFF optimizations).
5.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.15.9. Finished OPT passes. (There is nothing left to do.)
5.16. Executing MEMORY pass.
5.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
5.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
5.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
5.16.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
5.16.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
5.16.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.16.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
5.16.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
5.16.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.16.10. Executing MEMORY_COLLECT pass (generating $mem cells).
5.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.18. Executing OPT pass (performing simple optimizations).
5.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
<suppressed ~6 debug messages>
5.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.18.3. Executing OPT_DFF pass (perform DFF optimizations).
5.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.18.5. Finished fast OPT passes.
5.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
5.20. Executing OPT pass (performing simple optimizations).
5.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cntr_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
5.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \cntr_example.
Performed a total of 0 changes.
5.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.20.6. Executing OPT_SHARE pass.
5.20.7. Executing OPT_DFF pass (perform DFF optimizations).
5.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
5.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.20.10. Finished OPT passes. (There is nothing left to do.)
5.21. Executing TECHMAP pass (map to technology primitives).
5.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
5.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$ce0ec84be7047712840b0952f343ee9e63ef75d1\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $and.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000010100 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
No more expansions possible.
<suppressed ~675 debug messages>
5.22. Executing OPT pass (performing simple optimizations).
5.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
<suppressed ~555 debug messages>
5.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.
5.22.3. Executing OPT_DFF pass (perform DFF optimizations).
5.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
Removed 410 unused cells and 440 unused wires.
<suppressed ~411 debug messages>
5.22.5. Finished fast OPT passes.
5.23. Executing ABC pass (technology mapping using ABC).
5.23.1. Extracting gate netlist of module `\cntr_example' to `<abc-temp-dir>/input.blif'..
Extracted 30 gates and 50 wires to a netlist network with 20 inputs and 20 outputs.
5.23.1.1. Executing ABC.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_library <abc-temp-dir>/stdcells.genlib
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash
ABC: + dretime
ABC: + map
ABC: + write_blif <abc-temp-dir>/output.blif
5.23.1.2. Re-integrating ABC results.
ABC RESULTS: NOT cells: 5
ABC RESULTS: NAND cells: 5
ABC RESULTS: XNOR cells: 5
ABC RESULTS: ANDNOT cells: 5
ABC RESULTS: XOR cells: 10
ABC RESULTS: internal signals: 10
ABC RESULTS: input signals: 20
ABC RESULTS: output signals: 20
Removing temp directory.
5.24. Executing OPT pass (performing simple optimizations).
5.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
5.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
5.24.3. Executing OPT_DFF pass (perform DFF optimizations).
5.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
Removed 0 unused cells and 45 unused wires.
<suppressed ~1 debug messages>
5.24.5. Finished fast OPT passes.
5.25. Executing HIERARCHY pass (managing design hierarchy).
5.25.1. Analyzing design hierarchy..
Top module: \cntr_example
5.25.2. Analyzing design hierarchy..
Top module: \cntr_example
Removed 0 unused modules.
5.26. Printing statistics.
=== cntr_example ===
Number of wires: 40
Number of wire bits: 362
Number of public wires: 20
Number of public wire bits: 152
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 50
$_ANDNOT_ 5
$_NAND_ 5
$_NOT_ 5
$_SDFF_PN0_ 20
$_XNOR_ 5
$_XOR_ 10
5.27. Executing CHECK pass (checking for obvious problems).
Checking module cntr_example...
Found and reported 0 problems.
6. Generating Graphviz representation of design.
Writing dot description to `/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/synthesis/post_techmap.dot'.
Dumping module cntr_example to page 1.
Warning: WIDTHLABEL \cntr_3.out3 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.X [0] 1
Warning: WIDTHLABEL \cntr_5.out5 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.X [0] 1
Warning: WIDTHLABEL \cntr_2.out2 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.X [0] 1
Warning: WIDTHLABEL \cntr_4.out4 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.X [0] 1
Warning: WIDTHLABEL \cntr_1.out1 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.X [0] 1
Warning: WIDTHLABEL \cntr_2.out2 [1] 1
Warning: WIDTHLABEL \cntr_2.out2 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [1] 1
Warning: WIDTHLABEL \cntr_2.out2 [1] 1
Warning: WIDTHLABEL \cntr_2.out2 [0] 1
Warning: WIDTHLABEL \cntr_2.out2 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [2] 1
Warning: WIDTHLABEL \cntr_2.out2 [2] 1
Warning: WIDTHLABEL \cntr_2.out2 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [3] 1
Warning: WIDTHLABEL \cntr_3.out3 [1] 1
Warning: WIDTHLABEL \cntr_3.out3 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [1] 1
Warning: WIDTHLABEL \cntr_3.out3 [1] 1
Warning: WIDTHLABEL \cntr_3.out3 [0] 1
Warning: WIDTHLABEL \cntr_3.out3 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [2] 1
Warning: WIDTHLABEL \cntr_3.out3 [2] 1
Warning: WIDTHLABEL \cntr_3.out3 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [3] 1
Warning: WIDTHLABEL \cntr_4.out4 [1] 1
Warning: WIDTHLABEL \cntr_4.out4 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [1] 1
Warning: WIDTHLABEL \cntr_4.out4 [1] 1
Warning: WIDTHLABEL \cntr_4.out4 [0] 1
Warning: WIDTHLABEL \cntr_4.out4 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [2] 1
Warning: WIDTHLABEL \cntr_4.out4 [2] 1
Warning: WIDTHLABEL \cntr_4.out4 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [3] 1
Warning: WIDTHLABEL \cntr_1.out1 [1] 1
Warning: WIDTHLABEL \cntr_1.out1 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [1] 1
Warning: WIDTHLABEL \cntr_1.out1 [1] 1
Warning: WIDTHLABEL \cntr_1.out1 [0] 1
Warning: WIDTHLABEL \cntr_1.out1 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [2] 1
Warning: WIDTHLABEL \cntr_1.out1 [2] 1
Warning: WIDTHLABEL \cntr_1.out1 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [3] 1
Warning: WIDTHLABEL \cntr_5.out5 [1] 1
Warning: WIDTHLABEL \cntr_5.out5 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [1] 1
Warning: WIDTHLABEL \cntr_5.out5 [1] 1
Warning: WIDTHLABEL \cntr_5.out5 [0] 1
Warning: WIDTHLABEL \cntr_5.out5 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [2] 1
Warning: WIDTHLABEL \cntr_5.out5 [2] 1
Warning: WIDTHLABEL \cntr_5.out5 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.X [0] 1
Warning: WIDTHLABEL \cntr_5.out5 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [1] 1
Warning: WIDTHLABEL \cntr_5.out5 [1] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [2] 1
Warning: WIDTHLABEL \cntr_5.out5 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$78.Y [3] 1
Warning: WIDTHLABEL \cntr_5.out5 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.X [0] 1
Warning: WIDTHLABEL \cntr_1.out1 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [1] 1
Warning: WIDTHLABEL \cntr_1.out1 [1] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [2] 1
Warning: WIDTHLABEL \cntr_1.out1 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$66.Y [3] 1
Warning: WIDTHLABEL \cntr_1.out1 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.X [0] 1
Warning: WIDTHLABEL \cntr_2.out2 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [1] 1
Warning: WIDTHLABEL \cntr_2.out2 [1] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [2] 1
Warning: WIDTHLABEL \cntr_2.out2 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$69.Y [3] 1
Warning: WIDTHLABEL \cntr_2.out2 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.X [0] 1
Warning: WIDTHLABEL \cntr_3.out3 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [1] 1
Warning: WIDTHLABEL \cntr_3.out3 [1] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [2] 1
Warning: WIDTHLABEL \cntr_3.out3 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.Y [3] 1
Warning: WIDTHLABEL \cntr_3.out3 [3] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.X [0] 1
Warning: WIDTHLABEL \cntr_4.out4 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [1] 1
Warning: WIDTHLABEL \cntr_4.out4 [1] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [2] 1
Warning: WIDTHLABEL \cntr_4.out4 [2] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$75.Y [3] 1
Warning: WIDTHLABEL \cntr_4.out4 [3] 1
7. Executing SHARE pass (SAT-based resource sharing).
8. Executing OPT pass (performing simple optimizations).
8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cntr_example..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \cntr_example.
Performed a total of 0 changes.
8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cntr_example'.
Removed a total of 0 cells.
8.6. Executing OPT_DFF pass (perform DFF optimizations).
8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module cntr_example.
8.9. Finished OPT passes. (There is nothing left to do.)
9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
Removed 0 unused cells and 17 unused wires.
<suppressed ~17 debug messages>
10. Printing statistics.
=== cntr_example ===
Number of wires: 23
Number of wire bits: 250
Number of public wires: 3
Number of public wire bits: 40
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 50
$_ANDNOT_ 5
$_NAND_ 5
$_NOT_ 5
$_SDFF_PN0_ 20
$_XNOR_ 5
$_XOR_ 10
11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell gf180mcu_fd_sc_mcu7t5v0__dffnq_1 (noninv, pins=3, area=65.86) is a direct match for cell type $_DFF_N_.
cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (noninv, pins=3, area=63.66) is a direct match for cell type $_DFF_P_.
cell gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 (noninv, pins=4, area=74.64) is a direct match for cell type $_DFF_NN0_.
cell gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 (noninv, pins=4, area=79.03) is a direct match for cell type $_DFF_NN1_.
cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 (noninv, pins=4, area=74.64) is a direct match for cell type $_DFF_PN0_.
cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 (noninv, pins=4, area=79.03) is a direct match for cell type $_DFF_PN1_.
cell gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 (noninv, pins=5, area=94.39) is a direct match for cell type $_DFFSR_NNN_.
cell gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 (noninv, pins=5, area=85.61) is a direct match for cell type $_DFFSR_PNN_.
final dff cell mappings:
\gf180mcu_fd_sc_mcu7t5v0__dffnq_1 _DFF_N_ (.CLKN( C), .D( D), .Q( Q));
\gf180mcu_fd_sc_mcu7t5v0__dffq_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
\gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 _DFF_NN0_ (.CLKN( C), .D( D), .Q( Q), .RN( R));
\gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 _DFF_NN1_ (.CLKN( C), .D( D), .Q( Q), .SETN( R));
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RN( R));
\gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SETN( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
\gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 _DFFSR_NNN_ (.CLKN( C), .D( D), .Q( Q), .RN( R), .SETN( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
\gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .RN( R), .SETN( S));
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\cntr_example':
mapped 20 $_DFF_P_ cells to \gf180mcu_fd_sc_mcu7t5v0__dffq_1 cells.
12. Printing statistics.
=== cntr_example ===
Number of wires: 43
Number of wire bits: 270
Number of public wires: 3
Number of public wire bits: 40
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 70
$_ANDNOT_ 5
$_MUX_ 20
$_NAND_ 5
$_NOT_ 5
$_XNOR_ 5
$_XOR_ 10
gf180mcu_fd_sc_mcu7t5v0__dffq_1 20
[INFO]: USING STRATEGY AREA 0
13. Executing ABC pass (technology mapping using ABC).
13.1. Extracting gate netlist of module `\cntr_example' to `/tmp/yosys-abc-ZRRivd/input.blif'..
Extracted 50 gates and 72 wires to a netlist network with 21 inputs and 20 outputs.
13.1.1. Executing ABC.
Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-ZRRivd/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-ZRRivd/abc.script".
ABC:
ABC: + read_blif /tmp/yosys-abc-ZRRivd/input.blif
ABC: + read_lib -w /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/synthesis/trimmed.lib
ABC: Parsing finished successfully. Parsing time = 0.11 sec
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__antenna" without logic function.
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_3".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_12".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_16".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_4".
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__endcap" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_16" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_32" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_64" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__filltie" without logic function.
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__hold".
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_3".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_12".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_16".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_4".
ABC: Library "gf180mcuC_merged" from "/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/synthesis/trimmed.lib" has 143 cells (72 skipped: 36 seq; 15 tri-state; 21 no func; 0 dont_use). Time = 0.21 sec
ABC: Memory = 23.60 MB. Time = 0.21 sec
ABC: Warning: Detected 6 multi-output gates (for example, "gf180mcu_fd_sc_mcu7t5v0__addf_1").
ABC: + read_constr -v /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/synthesis/synthesis.sdc
ABC: Setting driving cell to be "gf180mcu_fd_sc_mcu7t5v0__inv_1".
ABC: Setting output load to be 72.910004.
ABC: + read_constr /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/synthesis/synthesis.sdc
ABC: + fx
ABC: + mfs
ABC: + strash
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + rewrite -z
ABC: + balance
ABC: + refactor -z
ABC: + rewrite -z
ABC: + balance
ABC: + retime -D -D 65000 -M 5
ABC: + scleanup
ABC: Error: The network is combinational.
ABC: + fraig_store
ABC: + balance
ABC: + fraig_store
ABC: + balance
ABC: + rewrite
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + rewrite -z
ABC: + balance
ABC: + refactor -z
ABC: + rewrite -z
ABC: + balance
ABC: + fraig_store
ABC: + balance
ABC: + rewrite
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + rewrite -z
ABC: + balance
ABC: + refactor -z
ABC: + rewrite -z
ABC: + balance
ABC: + fraig_store
ABC: + balance
ABC: + rewrite
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + rewrite -z
ABC: + balance
ABC: + refactor -z
ABC: + rewrite -z
ABC: + balance
ABC: + fraig_store
ABC: + fraig_restore
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
ABC: + retime -D -D 65000
ABC: + &get -n
ABC: + &st
ABC: + &dch
ABC: + &nf
ABC: + &put
ABC: + buffer -N 4 -S 3000
ABC: + upsize -D 65000
ABC: Current delay (2030.76 ps) does not exceed the target delay (65000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 65000
ABC: + stime -p
ABC: WireLoad = "none" Gates = 56 ( 19.6 %) Cap = 26.2 ff ( 13.9 %) Area = 864.91 ( 73.2 %) Delay = 2379.40 ps ( 32.1 %)
ABC: Path 0 -- 21 : 0 2 pi A = 0.00 Df = 56.5 -21.5 ps S = 144.8 ps Cin = 0.0 ff Cout = 5.7 ff Cmax = 0.0 ff G = 0
ABC: Path 1 -- 43 : 1 4 gf180mcu_fd_sc_mcu7t5v0__buf_1 A = 13.17 Df = 386.0 -31.0 ps S = 329.9 ps Cin = 2.9 ff Cout = 16.7 ff Cmax = 238.8 ff G = 579
ABC: Path 2 -- 44 : 1 4 gf180mcu_fd_sc_mcu7t5v0__clkinv_1 A = 8.78 Df = 633.3 -50.1 ps S = 297.4 ps Cin = 4.2 ff Cout = 14.7 ff Cmax = 228.4 ff G = 348
ABC: Path 3 -- 55 : 1 4 gf180mcu_fd_sc_mcu7t5v0__buf_1 A = 13.17 Df =1027.6 -83.4 ps S = 347.4 ps Cin = 2.9 ff Cout = 17.7 ff Cmax = 238.8 ff G = 615
ABC: Path 4 -- 89 : 2 1 gf180mcu_fd_sc_mcu7t5v0__nor2_1 A = 13.17 Df =2379.4 -699.1 ps S =2308.5 ps Cin = 4.4 ff Cout = 72.9 ff Cmax = 125.1 ff G = 1671
ABC: Start-point = pi20 (\wb_rst_i). End-point = po16 ($auto$rtlil.cc:2560:MuxGate$1354).
ABC: + print_stats -m
ABC: netlist : i/o = 21/ 20 lat = 0 nd = 56 edge = 121 area =864.88 delay = 4.00 lev = 4
ABC: + write_blif /tmp/yosys-abc-ZRRivd/output.blif
13.1.2. Re-integrating ABC results.
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__clkinv_1 cells: 1
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__buf_1 cells: 5
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 cells: 5
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__oai21_1 cells: 5
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 cells: 10
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nand3_1 cells: 5
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nand2_1 cells: 5
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__xor2_1 cells: 5
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nor2_1 cells: 15
ABC RESULTS: internal signals: 31
ABC RESULTS: input signals: 21
ABC RESULTS: output signals: 20
Removing temp directory.
14. Executing SETUNDEF pass (replace undef values with defined constants).
15. Executing HILOMAP pass (mapping to constant drivers).
16. Executing SPLITNETS pass (splitting up multi-bit signals).
17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
Removed 0 unused cells and 269 unused wires.
<suppressed ~1 debug messages>
18. Executing INSBUF pass (insert buffer cells for connected wires).
19. Executing CHECK pass (checking for obvious problems).
Checking module cntr_example...
Warning: Wire cntr_example.\io_out [37] is used but has no driver.
Warning: Wire cntr_example.\io_out [36] is used but has no driver.
Warning: Wire cntr_example.\io_out [35] is used but has no driver.
Warning: Wire cntr_example.\io_out [34] is used but has no driver.
Warning: Wire cntr_example.\io_out [33] is used but has no driver.
Warning: Wire cntr_example.\io_out [32] is used but has no driver.
Warning: Wire cntr_example.\io_out [31] is used but has no driver.
Warning: Wire cntr_example.\io_out [30] is used but has no driver.
Warning: Wire cntr_example.\io_out [29] is used but has no driver.
Warning: Wire cntr_example.\io_out [28] is used but has no driver.
Warning: Wire cntr_example.\io_out [27] is used but has no driver.
Warning: Wire cntr_example.\io_out [26] is used but has no driver.
Warning: Wire cntr_example.\io_out [25] is used but has no driver.
Warning: Wire cntr_example.\io_out [24] is used but has no driver.
Warning: Wire cntr_example.\io_out [23] is used but has no driver.
Warning: Wire cntr_example.\io_out [22] is used but has no driver.
Warning: Wire cntr_example.\io_out [21] is used but has no driver.
Warning: Wire cntr_example.\io_out [20] is used but has no driver.
Warning: Wire cntr_example.\io_out [19] is used but has no driver.
Warning: Wire cntr_example.\io_out [18] is used but has no driver.
Warning: Wire cntr_example.\io_out [17] is used but has no driver.
Warning: Wire cntr_example.\io_out [16] is used but has no driver.
Warning: Wire cntr_example.\io_out [15] is used but has no driver.
Warning: Wire cntr_example.\io_out [14] is used but has no driver.
Warning: Wire cntr_example.\io_out [13] is used but has no driver.
Warning: Wire cntr_example.\io_out [12] is used but has no driver.
Warning: Wire cntr_example.\io_out [11] is used but has no driver.
Warning: Wire cntr_example.\io_out [10] is used but has no driver.
Warning: Wire cntr_example.\io_out [9] is used but has no driver.
Warning: Wire cntr_example.\io_out [8] is used but has no driver.
Warning: Wire cntr_example.\io_out [7] is used but has no driver.
Warning: Wire cntr_example.\io_out [6] is used but has no driver.
Warning: Wire cntr_example.\io_out [5] is used but has no driver.
Warning: Wire cntr_example.\io_out [4] is used but has no driver.
Warning: Wire cntr_example.\io_out [3] is used but has no driver.
Warning: Wire cntr_example.\io_out [2] is used but has no driver.
Warning: Wire cntr_example.\io_out [1] is used but has no driver.
Warning: Wire cntr_example.\io_out [0] is used but has no driver.
Found and reported 38 problems.
20. Printing statistics.
=== cntr_example ===
Number of wires: 59
Number of wire bits: 96
Number of public wires: 3
Number of public wire bits: 40
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 94
gf180mcu_fd_sc_mcu7t5v0__aoi21_1 10
gf180mcu_fd_sc_mcu7t5v0__buf_1 5
gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 5
gf180mcu_fd_sc_mcu7t5v0__clkinv_1 1
gf180mcu_fd_sc_mcu7t5v0__dffq_1 20
gf180mcu_fd_sc_mcu7t5v0__nand2_1 5
gf180mcu_fd_sc_mcu7t5v0__nand3_1 5
gf180mcu_fd_sc_mcu7t5v0__nor2_1 15
gf180mcu_fd_sc_mcu7t5v0__oai21_1 5
gf180mcu_fd_sc_mcu7t5v0__tiel 18
gf180mcu_fd_sc_mcu7t5v0__xor2_1 5
Chip area for module '\cntr_example': 2296.179200
21. Executing Verilog backend.
21.1. Executing BMUXMAP pass.
21.2. Executing DEMUXMAP pass.
Dumping module `\cntr_example'.
Warnings: 88 unique messages, 166 total
End of script. Logfile hash: db03072174, CPU: user 1.38s system 0.02s, MEM: 58.25 MB peak
Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
Time spent: 29% 4x stat (0 sec), 29% 1x dfflibmap (0 sec), ...