| OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.07 0.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 0.54 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.87 2.18 2.72 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.18 net21 (net) |
| 2.88 0.06 2.78 ^ fanout23/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.71 0.53 3.31 ^ fanout23/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.04 net23 (net) |
| 0.71 0.00 3.31 ^ _095_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 1.35 0.90 4.20 v _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 2 0.19 _013_ (net) |
| 1.36 0.07 4.27 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4.27 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 0.60 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.85 clock uncertainty |
| -0.06 0.79 clock reconvergence pessimism |
| -0.27 0.53 library hold time |
| 0.53 data required time |
| ----------------------------------------------------------------------------- |
| 0.53 data required time |
| -4.27 data arrival time |
| ----------------------------------------------------------------------------- |
| 3.74 slack (MET) |
| |
| |
| Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.07 0.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 0.54 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.80 1.61 2.15 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.19 net8 (net) |
| 1.81 0.06 2.21 v _110_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.38 0.66 2.88 ^ _110_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.01 _055_ (net) |
| 0.38 0.00 2.88 ^ _111_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1.93 1.22 4.10 v _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.14 _019_ (net) |
| 1.93 0.04 4.14 v _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4.14 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 0.60 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.85 clock uncertainty |
| -0.06 0.79 clock reconvergence pessimism |
| -0.41 0.39 library hold time |
| 0.39 data required time |
| ----------------------------------------------------------------------------- |
| 0.39 data required time |
| -4.14 data arrival time |
| ----------------------------------------------------------------------------- |
| 3.75 slack (MET) |
| |
| |
| Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.07 0.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.05 clknet_1_1__leaf_wb_clk_i (net) |
| 0.12 0.00 0.55 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.07 1.75 2.30 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.22 net9 (net) |
| 2.08 0.08 2.38 v _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.50 0.96 3.34 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.05 _020_ (net) |
| 0.50 0.00 3.34 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 1.90 1.46 4.81 ^ _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 2 0.16 _001_ (net) |
| 1.91 0.05 4.86 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4.86 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 0.60 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.85 clock uncertainty |
| -0.03 0.82 clock reconvergence pessimism |
| 0.14 0.96 library hold time |
| 0.96 data required time |
| ----------------------------------------------------------------------------- |
| 0.96 data required time |
| -4.86 data arrival time |
| ----------------------------------------------------------------------------- |
| 3.90 slack (MET) |
| |
| |
| Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.07 0.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 0.54 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.20 1.82 2.36 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.23 net6 (net) |
| 2.21 0.08 2.45 v fanout22/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.46 0.96 3.40 v fanout22/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.04 net22 (net) |
| 0.46 0.00 3.40 v _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.38 0.34 3.74 ^ _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.01 _051_ (net) |
| 0.38 0.00 3.74 ^ _105_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 1.17 0.76 4.50 v _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 2 0.16 _017_ (net) |
| 1.18 0.05 4.55 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4.55 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 0.60 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.85 clock uncertainty |
| -0.06 0.79 clock reconvergence pessimism |
| -0.22 0.57 library hold time |
| 0.57 data required time |
| ----------------------------------------------------------------------------- |
| 0.57 data required time |
| -4.55 data arrival time |
| ----------------------------------------------------------------------------- |
| 3.98 slack (MET) |
| |
| |
| Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.07 0.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.05 clknet_1_1__leaf_wb_clk_i (net) |
| 0.12 0.00 0.55 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.95 1.68 2.23 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.20 net13 (net) |
| 1.96 0.07 2.30 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.76 1.10 3.41 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.07 net25 (net) |
| 0.76 0.00 3.41 v _074_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.38 0.38 3.79 ^ _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.01 _033_ (net) |
| 0.38 0.00 3.79 ^ _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 1.22 0.79 4.58 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2) |
| 2 0.17 _005_ (net) |
| 1.23 0.06 4.63 v _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4.63 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.15 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.05 clknet_1_1__leaf_wb_clk_i (net) |
| 0.12 0.00 0.61 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.86 clock uncertainty |
| -0.06 0.80 clock reconvergence pessimism |
| -0.23 0.57 library hold time |
| 0.57 data required time |
| ----------------------------------------------------------------------------- |
| 0.57 data required time |
| -4.63 data arrival time |
| ----------------------------------------------------------------------------- |
| 4.06 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.16 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.01 wb_rst_i (net) |
| 0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 4 0.34 net1 (net) |
| 2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 8 0.03 _021_ (net) |
| 0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.40 0.00 16.63 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 10.13 6.14 22.77 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.35 _007_ (net) |
| 10.13 0.15 22.92 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 22.92 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.15 0.07 65.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 65.54 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 65.29 clock uncertainty |
| 0.00 65.29 clock reconvergence pessimism |
| 0.70 65.99 library setup time |
| 65.99 data required time |
| ----------------------------------------------------------------------------- |
| 65.99 data required time |
| -22.92 data arrival time |
| ----------------------------------------------------------------------------- |
| 43.07 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.16 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.01 wb_rst_i (net) |
| 0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 4 0.34 net1 (net) |
| 2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 8 0.03 _021_ (net) |
| 0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _023_ (net) |
| 0.34 0.00 16.59 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 7.73 4.70 21.29 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.26 _004_ (net) |
| 7.73 0.11 21.40 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 21.40 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.15 0.07 65.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 65.54 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 65.29 clock uncertainty |
| 0.00 65.29 clock reconvergence pessimism |
| 0.43 65.72 library setup time |
| 65.72 data required time |
| ----------------------------------------------------------------------------- |
| 65.72 data required time |
| -21.40 data arrival time |
| ----------------------------------------------------------------------------- |
| 44.32 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.16 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.01 wb_rst_i (net) |
| 0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 4 0.34 net1 (net) |
| 2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 8 0.03 _021_ (net) |
| 0.62 0.00 15.72 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.56 0.56 16.29 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 8 0.03 _027_ (net) |
| 0.56 0.00 16.29 ^ _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.30 0.16 16.45 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.01 _042_ (net) |
| 0.30 0.00 16.45 v _089_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 7.76 4.71 21.17 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.27 _010_ (net) |
| 7.77 0.11 21.28 ^ _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 21.28 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.15 0.07 65.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.05 clknet_1_1__leaf_wb_clk_i (net) |
| 0.12 0.00 65.55 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 65.30 clock uncertainty |
| 0.00 65.30 clock reconvergence pessimism |
| 0.43 65.73 library setup time |
| 65.73 data required time |
| ----------------------------------------------------------------------------- |
| 65.73 data required time |
| -21.28 data arrival time |
| ----------------------------------------------------------------------------- |
| 44.45 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.16 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.01 wb_rst_i (net) |
| 0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 4 0.34 net1 (net) |
| 2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 8 0.03 _021_ (net) |
| 0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.40 0.00 16.63 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 7.31 4.47 21.10 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.25 _011_ (net) |
| 7.32 0.10 21.20 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 21.20 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.15 0.07 65.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 65.54 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 65.29 clock uncertainty |
| 0.00 65.29 clock reconvergence pessimism |
| 0.38 65.67 library setup time |
| 65.67 data required time |
| ----------------------------------------------------------------------------- |
| 65.67 data required time |
| -21.20 data arrival time |
| ----------------------------------------------------------------------------- |
| 44.47 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.16 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.01 wb_rst_i (net) |
| 0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 4 0.34 net1 (net) |
| 2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 8 0.03 _021_ (net) |
| 0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _023_ (net) |
| 0.34 0.00 16.59 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 7.20 4.38 20.97 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.25 _012_ (net) |
| 7.20 0.10 21.08 ^ _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 21.08 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.15 0.07 65.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.05 clknet_1_1__leaf_wb_clk_i (net) |
| 0.12 0.00 65.55 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 65.30 clock uncertainty |
| 0.00 65.30 clock reconvergence pessimism |
| 0.37 65.67 library setup time |
| 65.67 data required time |
| ----------------------------------------------------------------------------- |
| 65.67 data required time |
| -21.08 data arrival time |
| ----------------------------------------------------------------------------- |
| 44.59 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.16 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.01 wb_rst_i (net) |
| 0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 4 0.34 net1 (net) |
| 2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 8 0.03 _021_ (net) |
| 0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.40 0.00 16.63 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 10.13 6.14 22.77 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.35 _007_ (net) |
| 10.13 0.15 22.92 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 22.92 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.15 0.07 65.07 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.11 0.00 65.54 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 65.29 clock uncertainty |
| 0.00 65.29 clock reconvergence pessimism |
| 0.70 65.99 library setup time |
| 65.99 data required time |
| ----------------------------------------------------------------------------- |
| 65.99 data required time |
| -22.92 data arrival time |
| ----------------------------------------------------------------------------- |
| 43.07 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| max slew |
| |
| Pin Limit Slew Slack |
| ------------------------------------------------------------ |
| ANTENNA__119__D/I 4.00 10.13 -6.13 (VIOLATED) |
| _119_/D 4.00 10.13 -6.13 (VIOLATED) |
| _081_/ZN 4.00 10.13 -6.13 (VIOLATED) |
| ANTENNA__122__D/I 4.00 7.77 -3.77 (VIOLATED) |
| _122_/D 4.00 7.77 -3.77 (VIOLATED) |
| _089_/ZN 4.00 7.76 -3.76 (VIOLATED) |
| ANTENNA__116__D/I 4.00 7.73 -3.73 (VIOLATED) |
| _116_/D 4.00 7.73 -3.73 (VIOLATED) |
| _073_/ZN 4.00 7.73 -3.73 (VIOLATED) |
| ANTENNA__123__D/I 4.00 7.32 -3.32 (VIOLATED) |
| _123_/D 4.00 7.32 -3.32 (VIOLATED) |
| _091_/ZN 4.00 7.31 -3.31 (VIOLATED) |
| ANTENNA__126__D/I 4.00 7.20 -3.20 (VIOLATED) |
| _126_/D 4.00 7.20 -3.20 (VIOLATED) |
| _124_/D 4.00 7.20 -3.20 (VIOLATED) |
| ANTENNA__124__D/I 4.00 7.20 -3.20 (VIOLATED) |
| _099_/ZN 4.00 7.20 -3.20 (VIOLATED) |
| _093_/ZN 4.00 7.20 -3.20 (VIOLATED) |
| ANTENNA__115__D/I 4.00 6.98 -2.98 (VIOLATED) |
| _115_/D 4.00 6.98 -2.98 (VIOLATED) |
| _071_/ZN 4.00 6.98 -2.98 (VIOLATED) |
| output2/I 4.00 6.34 -2.34 (VIOLATED) |
| ANTENNA_output2_I/I 4.00 6.34 -2.34 (VIOLATED) |
| ANTENNA__072__I/I 4.00 6.34 -2.34 (VIOLATED) |
| _072_/I 4.00 6.34 -2.34 (VIOLATED) |
| ANTENNA__077__A1/I 4.00 6.34 -2.34 (VIOLATED) |
| _077_/A1 4.00 6.34 -2.34 (VIOLATED) |
| _116_/Q 4.00 6.32 -2.32 (VIOLATED) |
| output16/I 4.00 6.07 -2.07 (VIOLATED) |
| ANTENNA_output16_I/I 4.00 6.07 -2.07 (VIOLATED) |
| _082_/I 4.00 6.07 -2.07 (VIOLATED) |
| ANTENNA__082__I/I 4.00 6.07 -2.07 (VIOLATED) |
| _087_/A1 4.00 6.07 -2.07 (VIOLATED) |
| ANTENNA__087__A1/I 4.00 6.07 -2.07 (VIOLATED) |
| _120_/Q 4.00 6.05 -2.05 (VIOLATED) |
| ANTENNA__127__D/I 4.00 5.85 -1.85 (VIOLATED) |
| _127_/D 4.00 5.85 -1.85 (VIOLATED) |
| _101_/ZN 4.00 5.84 -1.84 (VIOLATED) |
| _087_/A2 4.00 5.74 -1.74 (VIOLATED) |
| ANTENNA__087__A2/I 4.00 5.74 -1.74 (VIOLATED) |
| ANTENNA_fanout24_I/I 4.00 5.74 -1.74 (VIOLATED) |
| fanout24/I 4.00 5.74 -1.74 (VIOLATED) |
| _121_/Q 4.00 5.73 -1.73 (VIOLATED) |
| ANTENNA__120__D/I 4.00 5.46 -1.46 (VIOLATED) |
| _120_/D 4.00 5.46 -1.46 (VIOLATED) |
| _083_/ZN 4.00 5.46 -1.46 (VIOLATED) |
| ANTENNA__128__D/I 4.00 5.39 -1.39 (VIOLATED) |
| _128_/D 4.00 5.39 -1.39 (VIOLATED) |
| _103_/ZN 4.00 5.39 -1.39 (VIOLATED) |
| ANTENNA__112__D/I 4.00 5.29 -1.29 (VIOLATED) |
| _112_/D 4.00 5.29 -1.29 (VIOLATED) |
| _060_/ZN 4.00 5.29 -1.29 (VIOLATED) |
| _114_/D 4.00 5.16 -1.16 (VIOLATED) |
| ANTENNA__114__D/I 4.00 5.16 -1.16 (VIOLATED) |
| _068_/ZN 4.00 5.15 -1.15 (VIOLATED) |
| output14/I 4.00 5.02 -1.02 (VIOLATED) |
| ANTENNA_output14_I/I 4.00 5.02 -1.02 (VIOLATED) |
| _076_/B 4.00 5.02 -1.02 (VIOLATED) |
| _077_/A3 4.00 5.02 -1.02 (VIOLATED) |
| ANTENNA__077__A3/I 4.00 5.02 -1.02 (VIOLATED) |
| ANTENNA__076__B/I 4.00 5.02 -1.02 (VIOLATED) |
| ANTENNA__121__D/I 4.00 5.02 -1.02 (VIOLATED) |
| _121_/D 4.00 5.02 -1.02 (VIOLATED) |
| _118_/Q 4.00 5.01 -1.01 (VIOLATED) |
| _085_/ZN 4.00 5.01 -1.01 (VIOLATED) |
| output11/I 4.00 4.90 -0.90 (VIOLATED) |
| ANTENNA_output11_I/I 4.00 4.90 -0.90 (VIOLATED) |
| _064_/B 4.00 4.90 -0.90 (VIOLATED) |
| ANTENNA__064__B/I 4.00 4.90 -0.90 (VIOLATED) |
| ANTENNA__066__A3/I 4.00 4.90 -0.90 (VIOLATED) |
| _066_/A3 4.00 4.90 -0.90 (VIOLATED) |
| _114_/Q 4.00 4.88 -0.88 (VIOLATED) |
| ANTENNA__118__D/I 4.00 4.75 -0.75 (VIOLATED) |
| _118_/D 4.00 4.75 -0.75 (VIOLATED) |
| _079_/ZN 4.00 4.74 -0.74 (VIOLATED) |
| output19/I 4.00 4.69 -0.69 (VIOLATED) |
| ANTENNA_output19_I/I 4.00 4.69 -0.69 (VIOLATED) |
| _090_/A1 4.00 4.69 -0.69 (VIOLATED) |
| ANTENNA__090__A1/I 4.00 4.69 -0.69 (VIOLATED) |
| _123_/Q 4.00 4.68 -0.68 (VIOLATED) |
| output7/I 4.00 4.65 -0.65 (VIOLATED) |
| ANTENNA_output7_I/I 4.00 4.65 -0.65 (VIOLATED) |
| _106_/B 4.00 4.65 -0.65 (VIOLATED) |
| ANTENNA__106__B/I 4.00 4.65 -0.65 (VIOLATED) |
| _107_/A3 4.00 4.65 -0.65 (VIOLATED) |
| ANTENNA__107__A3/I 4.00 4.65 -0.65 (VIOLATED) |
| _130_/Q 4.00 4.64 -0.64 (VIOLATED) |
| output20/I 4.00 4.62 -0.62 (VIOLATED) |
| ANTENNA_output20_I/I 4.00 4.62 -0.62 (VIOLATED) |
| ANTENNA__092__I/I 4.00 4.62 -0.62 (VIOLATED) |
| _092_/I 4.00 4.62 -0.62 (VIOLATED) |
| ANTENNA__097__A1/I 4.00 4.62 -0.62 (VIOLATED) |
| _097_/A1 4.00 4.62 -0.62 (VIOLATED) |
| _124_/Q 4.00 4.61 -0.61 (VIOLATED) |
| _130_/D 4.00 4.46 -0.46 (VIOLATED) |
| ANTENNA__130__D/I 4.00 4.46 -0.46 (VIOLATED) |
| _109_/ZN 4.00 4.46 -0.46 (VIOLATED) |
| output5/I 4.00 4.44 -0.44 (VIOLATED) |
| ANTENNA_output5_I/I 4.00 4.44 -0.44 (VIOLATED) |
| _107_/A1 4.00 4.44 -0.44 (VIOLATED) |
| ANTENNA__107__A1/I 4.00 4.44 -0.44 (VIOLATED) |
| ANTENNA__102__I/I 4.00 4.44 -0.44 (VIOLATED) |
| _102_/I 4.00 4.44 -0.44 (VIOLATED) |
| _128_/Q 4.00 4.43 -0.43 (VIOLATED) |
| output3/I 4.00 4.40 -0.40 (VIOLATED) |
| ANTENNA_output3_I/I 4.00 4.40 -0.40 (VIOLATED) |
| ANTENNA__096__B/I 4.00 4.40 -0.40 (VIOLATED) |
| _096_/B 4.00 4.40 -0.40 (VIOLATED) |
| _097_/A3 4.00 4.40 -0.40 (VIOLATED) |
| ANTENNA__097__A3/I 4.00 4.40 -0.40 (VIOLATED) |
| _126_/Q 4.00 4.39 -0.39 (VIOLATED) |
| _131_/D 4.00 4.22 -0.22 (VIOLATED) |
| ANTENNA__131__D/I 4.00 4.22 -0.22 (VIOLATED) |
| _111_/ZN 4.00 4.22 -0.22 (VIOLATED) |
| |
| max fanout |
| |
| Pin Limit Fanout Slack |
| --------------------------------------------------------- |
| clkbuf_1_1__f_wb_clk_i/Z 4 18 -14 (VIOLATED) |
| clkbuf_1_0__f_wb_clk_i/Z 4 11 -7 (VIOLATED) |
| _056_/Z 4 8 -4 (VIOLATED) |
| _057_/Z 4 8 -4 (VIOLATED) |
| _061_/Z 4 8 -4 (VIOLATED) |
| _065_/Z 4 8 -4 (VIOLATED) |
| _072_/Z 4 8 -4 (VIOLATED) |
| _082_/Z 4 8 -4 (VIOLATED) |
| _092_/Z 4 8 -4 (VIOLATED) |
| _102_/Z 4 8 -4 (VIOLATED) |
| fanout22/Z 4 8 -4 (VIOLATED) |
| fanout23/Z 4 8 -4 (VIOLATED) |
| fanout24/Z 4 8 -4 (VIOLATED) |
| fanout25/Z 4 8 -4 (VIOLATED) |
| fanout26/Z 4 8 -4 (VIOLATED) |
| _112_/Q 4 6 -2 (VIOLATED) |
| _114_/Q 4 6 -2 (VIOLATED) |
| _116_/Q 4 6 -2 (VIOLATED) |
| _118_/Q 4 6 -2 (VIOLATED) |
| _120_/Q 4 6 -2 (VIOLATED) |
| _122_/Q 4 6 -2 (VIOLATED) |
| _124_/Q 4 6 -2 (VIOLATED) |
| _126_/Q 4 6 -2 (VIOLATED) |
| _128_/Q 4 6 -2 (VIOLATED) |
| _130_/Q 4 6 -2 (VIOLATED) |
| |
| max capacitance |
| |
| Pin Limit Cap Slack |
| ------------------------------------------------------------ |
| _081_/ZN 0.13 0.35 -0.22 (VIOLATED) |
| _116_/Q 0.24 0.40 -0.16 (VIOLATED) |
| _120_/Q 0.24 0.38 -0.14 (VIOLATED) |
| _089_/ZN 0.13 0.27 -0.14 (VIOLATED) |
| _073_/ZN 0.13 0.26 -0.14 (VIOLATED) |
| _091_/ZN 0.13 0.25 -0.12 (VIOLATED) |
| _093_/ZN 0.13 0.25 -0.12 (VIOLATED) |
| _099_/ZN 0.13 0.25 -0.12 (VIOLATED) |
| _121_/Q 0.24 0.36 -0.12 (VIOLATED) |
| _071_/ZN 0.13 0.24 -0.11 (VIOLATED) |
| _085_/ZN 0.25 0.33 -0.09 (VIOLATED) |
| _118_/Q 0.24 0.31 -0.07 (VIOLATED) |
| _101_/ZN 0.13 0.20 -0.07 (VIOLATED) |
| _114_/Q 0.24 0.31 -0.07 (VIOLATED) |
| _083_/ZN 0.13 0.19 -0.06 (VIOLATED) |
| _103_/ZN 0.13 0.18 -0.06 (VIOLATED) |
| _060_/ZN 0.13 0.18 -0.05 (VIOLATED) |
| _123_/Q 0.24 0.29 -0.05 (VIOLATED) |
| _130_/Q 0.24 0.29 -0.05 (VIOLATED) |
| _068_/ZN 0.13 0.17 -0.05 (VIOLATED) |
| _124_/Q 0.24 0.29 -0.05 (VIOLATED) |
| _128_/Q 0.24 0.28 -0.04 (VIOLATED) |
| _079_/ZN 0.13 0.16 -0.04 (VIOLATED) |
| _126_/Q 0.24 0.27 -0.03 (VIOLATED) |
| _109_/ZN 0.13 0.15 -0.02 (VIOLATED) |
| _111_/ZN 0.13 0.14 -0.02 (VIOLATED) |
| |
| |
| =========================================================================== |
| max slew violation count 114 |
| max fanout violation count 25 |
| max cap violation count 26 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 43.07 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 3.74 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _118_/CLK ^ |
| 0.61 |
| _119_/CLK ^ |
| 0.54 -0.03 0.03 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 1.69e-04 1.08e-04 4.08e-09 2.77e-04 39.0% |
| Combinational 2.15e-04 2.16e-04 2.94e-06 4.34e-04 61.0% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 3.84e-04 3.24e-04 2.94e-06 7.12e-04 100.0% |
| 54.0% 45.6% 0.4% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 68361 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| [WARNING] Did not save OpenROAD database! |
| Writing SDF to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.sdf... |
| Writing timing model to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.lib... |
