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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 1d3409ba822566404d008bc08cdc60c11a44da62 / . / openlane / cntr_example / runs / cntr_example / logs / signoff / 21-rcx_mcsta.nom.log
blob: 9c30817d6682fcf071658f4db0f44891223b47e0 [file] [log] [blame]
OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
min_report
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
======================= Slowest Corner ===================================
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.01 2.82 3.79 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
3.01 0.06 3.85 v _110_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.69 1.15 5.00 ^ _110_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _055_ (net)
0.69 0.00 5.00 ^ _111_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.31 2.10 7.10 v _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
3.31 0.04 7.14 v _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.14 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-0.72 0.50 library hold time
0.50 data required time
-----------------------------------------------------------------------------
0.50 data required time
-7.14 data arrival time
-----------------------------------------------------------------------------
6.64 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.87 2.74 3.71 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
2.88 0.06 3.77 v fanout23/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.77 1.50 5.27 v fanout23/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net23 (net)
0.77 0.00 5.27 v _094_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.70 0.67 5.94 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _045_ (net)
0.70 0.00 5.94 ^ _095_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.30 1.49 7.43 v _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.19 _013_ (net)
2.31 0.07 7.50 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.50 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-0.47 0.75 library hold time
0.75 data required time
-----------------------------------------------------------------------------
0.75 data required time
-7.50 data arrival time
-----------------------------------------------------------------------------
6.75 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.46 3.07 4.05 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
3.47 0.08 4.13 v _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.86 1.68 5.81 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _020_ (net)
0.86 0.00 5.81 v _062_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.69 0.68 6.49 ^ _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _025_ (net)
0.69 0.00 6.49 ^ _063_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.02 1.34 7.83 v _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _001_ (net)
2.02 0.05 7.88 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.88 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.06 1.26 clock reconvergence pessimism
-0.39 0.87 library hold time
0.87 data required time
-----------------------------------------------------------------------------
0.87 data required time
-7.88 data arrival time
-----------------------------------------------------------------------------
7.01 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.67 3.18 4.15 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
3.68 0.08 4.23 v fanout22/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.78 1.67 5.90 v fanout22/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net22 (net)
0.78 0.00 5.90 v _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.66 0.62 6.52 ^ _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _051_ (net)
0.66 0.00 6.52 ^ _105_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.02 1.32 7.84 v _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _017_ (net)
2.02 0.05 7.90 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.90 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-0.39 0.83 library hold time
0.83 data required time
-----------------------------------------------------------------------------
0.83 data required time
-7.90 data arrival time
-----------------------------------------------------------------------------
7.07 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.25 2.95 3.93 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
3.26 0.07 4.01 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 1.91 5.91 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.08 net25 (net)
1.29 0.00 5.91 v _074_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.67 0.69 6.60 ^ _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _033_ (net)
0.67 0.00 6.60 ^ _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.10 1.38 7.98 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.17 _005_ (net)
2.11 0.06 8.03 v _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.03 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-0.41 0.82 library hold time
0.82 data required time
-----------------------------------------------------------------------------
0.82 data required time
-8.03 data arrival time
-----------------------------------------------------------------------------
7.21 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.84 2.74 3.71 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
2.85 0.05 3.76 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.64 1.07 4.83 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _049_ (net)
0.64 0.00 4.83 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.59 2.81 7.64 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.20 _015_ (net)
4.59 0.07 7.71 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.71 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-1.03 0.19 library hold time
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
-7.71 data arrival time
-----------------------------------------------------------------------------
7.52 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.65 3.72 4.69 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
4.66 0.11 4.81 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.84 1.17 5.98 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _052_ (net)
0.84 0.00 5.98 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.50 2.21 8.19 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.15 _018_ (net)
3.50 0.04 8.22 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.22 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-0.77 0.45 library hold time
0.45 data required time
-----------------------------------------------------------------------------
0.45 data required time
-8.22 data arrival time
-----------------------------------------------------------------------------
7.77 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.03 3.93 4.91 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
5.04 0.13 5.04 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.63 1.03 6.07 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _034_ (net)
0.63 0.00 6.07 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.72 2.29 8.36 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _006_ (net)
3.72 0.05 8.41 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.41 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-0.82 0.41 library hold time
0.41 data required time
-----------------------------------------------------------------------------
0.41 data required time
-8.41 data arrival time
-----------------------------------------------------------------------------
7.99 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.90 3.86 4.83 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
4.91 0.12 4.95 v _064_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.66 1.04 5.99 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _026_ (net)
0.66 0.00 5.99 ^ _068_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.04 2.48 8.47 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.17 _002_ (net)
4.05 0.06 8.52 v _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.52 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-0.90 0.32 library hold time
0.32 data required time
-----------------------------------------------------------------------------
0.32 data required time
-8.52 data arrival time
-----------------------------------------------------------------------------
8.21 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.36 3.02 4.00 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
3.36 0.07 4.07 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.65 0.84 4.92 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _040_ (net)
0.65 0.00 4.92 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.10 3.63 8.54 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.27 _010_ (net)
6.11 0.10 8.65 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.65 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-1.38 -0.14 library hold time
-0.14 data required time
-----------------------------------------------------------------------------
-0.14 data required time
-8.65 data arrival time
-----------------------------------------------------------------------------
8.79 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.90 4.38 5.36 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
5.91 0.08 5.44 ^ _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.40 1.02 6.46 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _020_ (net)
1.40 0.00 6.46 ^ _060_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.13 2.69 9.14 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _000_ (net)
4.14 0.06 9.21 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.21 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-0.92 0.32 library hold time
0.32 data required time
-----------------------------------------------------------------------------
0.32 data required time
-9.21 data arrival time
-----------------------------------------------------------------------------
8.89 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.62 3.16 4.14 v _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net12 (net)
3.63 0.08 4.22 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.78 1.35 5.57 ^ _070_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
0.78 0.00 5.57 ^ _071_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.48 3.34 8.91 v _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.24 _003_ (net)
5.49 0.08 9.00 v _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.00 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-1.23 0.00 library hold time
0.00 data required time
-----------------------------------------------------------------------------
0.00 data required time
-9.00 data arrival time
-----------------------------------------------------------------------------
9.00 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.40 3.59 4.57 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net3 (net)
4.41 0.10 4.68 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.60 0.93 5.61 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _046_ (net)
0.60 0.00 5.61 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.64 3.36 8.97 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _014_ (net)
5.65 0.09 9.06 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.06 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-1.27 -0.04 library hold time
-0.04 data required time
-----------------------------------------------------------------------------
-0.04 data required time
-9.06 data arrival time
-----------------------------------------------------------------------------
9.10 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.56 5.27 6.26 ^ _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
7.57 0.10 6.36 ^ _102_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.35 0.91 7.27 ^ _102_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 _050_ (net)
1.35 0.00 7.27 ^ _103_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.21 2.72 9.99 v _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _016_ (net)
4.22 0.07 10.06 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
10.06 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-0.94 0.30 library hold time
0.30 data required time
-----------------------------------------------------------------------------
0.30 data required time
-10.06 data arrival time
-----------------------------------------------------------------------------
9.76 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.36 3.02 4.00 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
3.36 0.07 4.07 v _087_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
1.32 1.35 5.42 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
2 0.01 _041_ (net)
1.32 0.00 5.42 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1.26 1.07 6.49 ^ _090_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.02 _043_ (net)
1.26 0.00 6.49 ^ _091_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.75 3.59 10.08 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _011_ (net)
5.75 0.09 10.17 v _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
10.17 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.06 1.26 clock reconvergence pessimism
-1.30 -0.04 library hold time
-0.04 data required time
-----------------------------------------------------------------------------
-0.04 data required time
-10.17 data arrival time
-----------------------------------------------------------------------------
10.21 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.83 2.73 3.70 v _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net15 (net)
2.83 0.05 3.75 v _080_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.89 1.24 4.99 ^ _080_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.01 _037_ (net)
0.89 0.00 4.99 ^ _081_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
8.00 4.75 9.75 v _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
8.01 0.13 9.88 v _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.88 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-1.81 -0.59 library hold time
-0.59 data required time
-----------------------------------------------------------------------------
-0.59 data required time
-9.88 data arrival time
-----------------------------------------------------------------------------
10.48 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.08 4.50 5.46 v _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
6.10 0.16 5.63 v _082_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.98 2.23 7.86 v _082_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _038_ (net)
0.98 0.00 7.86 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.70 0.73 8.59 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _039_ (net)
0.70 0.00 8.59 ^ _085_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
3.95 2.39 10.98 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.33 _009_ (net)
3.96 0.13 11.12 v _121_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
11.12 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.06 1.28 clock reconvergence pessimism
-0.88 0.40 library hold time
0.40 data required time
-----------------------------------------------------------------------------
0.40 data required time
-11.12 data arrival time
-----------------------------------------------------------------------------
10.71 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.87 5.43 6.41 ^ _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
7.88 0.12 6.53 ^ _092_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.45 0.95 7.48 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _044_ (net)
1.45 0.00 7.48 ^ _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.61 3.54 11.02 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _012_ (net)
5.61 0.09 11.11 v _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
11.11 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.34 clock uncertainty
-0.10 1.23 clock reconvergence pessimism
-1.26 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-11.11 data arrival time
-----------------------------------------------------------------------------
11.14 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.08 4.50 5.46 v _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
6.10 0.16 5.63 v _082_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.98 2.23 7.86 v _082_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _038_ (net)
0.98 0.00 7.86 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.86 5.60 13.46 ^ _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _008_ (net)
9.86 0.06 13.53 ^ _120_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
13.53 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
1.00 2.21 library hold time
2.21 data required time
-----------------------------------------------------------------------------
2.21 data required time
-13.53 data arrival time
-----------------------------------------------------------------------------
11.31 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
10.79 6.99 7.96 ^ _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
10.80 0.17 8.13 ^ _072_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.44 0.79 8.92 ^ _072_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _032_ (net)
1.44 0.00 8.93 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.02 3.77 12.70 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.26 _004_ (net)
6.03 0.10 12.80 v _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
12.80 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.32 clock uncertainty
-0.10 1.22 clock reconvergence pessimism
-1.36 -0.14 library hold time
-0.14 data required time
-----------------------------------------------------------------------------
-0.14 data required time
-12.80 data arrival time
-----------------------------------------------------------------------------
12.94 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.83 2.73 3.70 v _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net15 (net)
2.83 0.05 3.75 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.65 1.22 4.97 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[3] (net)
0.65 0.00 4.98 v io_out[3] (out)
4.98 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.98 data arrival time
-----------------------------------------------------------------------------
17.73 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.84 2.74 3.71 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
2.85 0.05 3.76 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.65 1.23 4.99 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[11] (net)
0.65 0.00 4.99 v io_out[11] (out)
4.99 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.99 data arrival time
-----------------------------------------------------------------------------
17.74 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.87 2.74 3.71 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
2.88 0.06 3.77 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.65 1.23 5.00 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[9] (net)
0.65 0.00 5.00 v io_out[9] (out)
5.00 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.00 data arrival time
-----------------------------------------------------------------------------
17.75 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.01 2.82 3.79 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
3.01 0.06 3.85 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.66 1.25 5.10 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[15] (net)
0.66 0.00 5.11 v io_out[15] (out)
5.11 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.11 data arrival time
-----------------------------------------------------------------------------
17.86 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.36 3.02 4.00 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
3.36 0.07 4.07 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.66 1.30 5.37 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[6] (net)
0.66 0.00 5.37 v io_out[6] (out)
5.37 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.37 data arrival time
-----------------------------------------------------------------------------
18.12 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.46 3.07 4.05 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
3.47 0.08 4.13 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.67 1.31 5.44 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[16] (net)
0.67 0.00 5.45 v io_out[16] (out)
5.45 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.45 data arrival time
-----------------------------------------------------------------------------
18.20 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.62 3.16 4.14 v _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net12 (net)
3.63 0.09 4.23 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.68 1.33 5.56 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[19] (net)
0.68 0.00 5.56 v io_out[19] (out)
5.56 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.56 data arrival time
-----------------------------------------------------------------------------
18.31 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.67 3.18 4.15 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
3.68 0.08 4.24 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.68 1.34 5.58 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[13] (net)
0.68 0.00 5.58 v io_out[13] (out)
5.58 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.58 data arrival time
-----------------------------------------------------------------------------
18.33 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.78 3.24 4.21 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.24 net10 (net)
3.79 0.09 4.30 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.68 1.35 5.65 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[17] (net)
0.68 0.00 5.65 v io_out[17] (out)
5.65 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.65 data arrival time
-----------------------------------------------------------------------------
18.40 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.40 3.59 4.57 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net3 (net)
4.41 0.10 4.68 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.69 1.43 6.10 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[10] (net)
0.69 0.00 6.10 v io_out[10] (out)
6.10 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.10 data arrival time
-----------------------------------------------------------------------------
18.85 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.44 3.61 4.60 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
4.45 0.10 4.70 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.69 1.43 6.13 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[12] (net)
0.69 0.00 6.13 v io_out[12] (out)
6.13 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.13 data arrival time
-----------------------------------------------------------------------------
18.88 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.62 3.70 4.69 v _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
4.63 0.12 4.80 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.70 1.45 6.25 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[8] (net)
0.70 0.00 6.26 v io_out[8] (out)
6.26 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.26 data arrival time
-----------------------------------------------------------------------------
19.01 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.65 3.72 4.69 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
4.66 0.11 4.81 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.70 1.46 6.26 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[14] (net)
0.70 0.00 6.26 v io_out[14] (out)
6.26 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.26 data arrival time
-----------------------------------------------------------------------------
19.01 slack (MET)
Startpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.69 3.74 4.71 v _123_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.29 net19 (net)
4.70 0.12 4.82 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.70 1.46 6.28 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[7] (net)
0.70 0.00 6.28 v io_out[7] (out)
6.28 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.28 data arrival time
-----------------------------------------------------------------------------
19.03 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.90 3.86 4.83 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
4.91 0.12 4.95 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.70 1.48 6.43 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[18] (net)
0.70 0.00 6.44 v io_out[18] (out)
6.44 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.44 data arrival time
-----------------------------------------------------------------------------
19.19 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.03 3.93 4.91 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
5.04 0.13 5.04 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.71 1.50 6.54 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[2] (net)
0.71 0.00 6.54 v io_out[2] (out)
6.54 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.54 data arrival time
-----------------------------------------------------------------------------
19.29 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.25 2.95 3.93 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
3.26 0.07 4.01 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 1.91 5.91 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.08 net25 (net)
1.29 0.00 5.92 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.61 0.97 6.89 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[1] (net)
0.61 0.00 6.89 v io_out[1] (out)
6.89 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-6.89 data arrival time
-----------------------------------------------------------------------------
19.64 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.08 4.50 5.46 v _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
6.10 0.17 5.63 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.73 1.61 7.24 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[4] (net)
0.73 0.00 7.24 v io_out[4] (out)
7.24 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-7.24 data arrival time
-----------------------------------------------------------------------------
19.99 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 0.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.97 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.35 4.65 5.61 v _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
6.36 0.18 5.79 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.73 1.63 7.42 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[0] (net)
0.73 0.00 7.42 v io_out[0] (out)
7.42 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-7.42 data arrival time
-----------------------------------------------------------------------------
20.17 slack (MET)
Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.12 0.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 0.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 0.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 0.98 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.74 4.32 5.31 v _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.36 net17 (net)
5.75 0.14 5.45 v fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.26 2.37 7.82 v fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net24 (net)
1.26 0.00 7.82 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.61 0.96 8.78 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[5] (net)
0.61 0.00 8.78 v io_out[5] (out)
8.78 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-8.78 data arrival time
-----------------------------------------------------------------------------
21.53 slack (MET)
======================= Typical Corner ===================================
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.87 2.18 2.72 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
2.88 0.06 2.78 ^ fanout23/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.71 0.53 3.31 ^ fanout23/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net23 (net)
0.71 0.00 3.31 ^ _095_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.35 0.90 4.20 v _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.19 _013_ (net)
1.36 0.07 4.27 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.27 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.27 0.53 library hold time
0.53 data required time
-----------------------------------------------------------------------------
0.53 data required time
-4.27 data arrival time
-----------------------------------------------------------------------------
3.74 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.80 1.61 2.15 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
1.81 0.06 2.21 v _110_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.38 0.66 2.88 ^ _110_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _055_ (net)
0.38 0.00 2.88 ^ _111_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.93 1.22 4.10 v _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
1.93 0.04 4.14 v _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.14 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.41 0.39 library hold time
0.39 data required time
-----------------------------------------------------------------------------
0.39 data required time
-4.14 data arrival time
-----------------------------------------------------------------------------
3.75 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.07 1.75 2.30 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
2.08 0.08 2.38 v _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.50 0.96 3.34 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _020_ (net)
0.50 0.00 3.34 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.90 1.46 4.81 ^ _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _001_ (net)
1.91 0.05 4.86 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.86 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.03 0.82 clock reconvergence pessimism
0.14 0.96 library hold time
0.96 data required time
-----------------------------------------------------------------------------
0.96 data required time
-4.86 data arrival time
-----------------------------------------------------------------------------
3.90 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.20 1.82 2.36 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
2.21 0.08 2.45 v fanout22/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.46 0.96 3.40 v fanout22/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net22 (net)
0.46 0.00 3.40 v _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.38 0.34 3.74 ^ _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _051_ (net)
0.38 0.00 3.74 ^ _105_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.17 0.76 4.50 v _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _017_ (net)
1.18 0.05 4.55 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.55 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.22 0.57 library hold time
0.57 data required time
-----------------------------------------------------------------------------
0.57 data required time
-4.55 data arrival time
-----------------------------------------------------------------------------
3.98 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.95 1.68 2.23 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
1.96 0.07 2.30 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.76 1.10 3.41 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net25 (net)
0.76 0.00 3.41 v _074_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.38 0.38 3.79 ^ _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _033_ (net)
0.38 0.00 3.79 ^ _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.22 0.79 4.58 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.17 _005_ (net)
1.23 0.06 4.63 v _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.63 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.23 0.57 library hold time
0.57 data required time
-----------------------------------------------------------------------------
0.57 data required time
-4.63 data arrival time
-----------------------------------------------------------------------------
4.06 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.71 1.56 2.11 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
1.71 0.05 2.16 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.35 0.62 2.78 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _049_ (net)
0.35 0.00 2.78 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.69 1.63 4.42 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.20 _015_ (net)
2.70 0.07 4.48 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.48 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.59 0.21 library hold time
0.21 data required time
-----------------------------------------------------------------------------
0.21 data required time
-4.48 data arrival time
-----------------------------------------------------------------------------
4.28 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.78 2.14 2.69 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
2.80 0.11 2.80 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.46 0.67 3.47 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _052_ (net)
0.46 0.00 3.47 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.04 1.29 4.76 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.15 _018_ (net)
2.04 0.04 4.79 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.79 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.43 0.36 library hold time
0.36 data required time
-----------------------------------------------------------------------------
0.36 data required time
-4.79 data arrival time
-----------------------------------------------------------------------------
4.43 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.01 2.26 2.81 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
3.03 0.13 2.93 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.34 0.59 3.52 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _034_ (net)
0.34 0.00 3.52 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.18 1.33 4.85 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _006_ (net)
2.19 0.05 4.91 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.91 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.47 0.33 library hold time
0.33 data required time
-----------------------------------------------------------------------------
0.33 data required time
-4.91 data arrival time
-----------------------------------------------------------------------------
4.57 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.93 2.22 2.76 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
2.95 0.12 2.88 v _064_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.36 0.60 3.48 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _026_ (net)
0.36 0.00 3.48 ^ _068_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.37 1.44 4.92 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.17 _002_ (net)
2.38 0.06 4.97 v _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.97 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-0.51 0.28 library hold time
0.28 data required time
-----------------------------------------------------------------------------
0.28 data required time
-4.97 data arrival time
-----------------------------------------------------------------------------
4.69 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.46 2.49 3.04 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
3.47 0.08 3.12 ^ _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.80 0.55 3.67 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _020_ (net)
0.80 0.00 3.67 ^ _060_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.42 1.55 5.21 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _000_ (net)
2.43 0.06 5.28 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.28 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.52 0.28 library hold time
0.28 data required time
-----------------------------------------------------------------------------
0.28 data required time
-5.28 data arrival time
-----------------------------------------------------------------------------
5.00 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.01 1.72 2.27 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
2.02 0.07 2.35 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.35 0.48 2.83 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _040_ (net)
0.35 0.00 2.83 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.58 2.10 4.93 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.27 _010_ (net)
3.59 0.10 5.03 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.03 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.79 0.01 library hold time
0.01 data required time
-----------------------------------------------------------------------------
0.01 data required time
-5.03 data arrival time
-----------------------------------------------------------------------------
5.03 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.17 1.81 2.36 v _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net12 (net)
2.18 0.08 2.44 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.42 0.78 3.22 ^ _070_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
0.42 0.00 3.22 ^ _071_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.22 1.94 5.16 v _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.24 _003_ (net)
3.22 0.08 5.25 v _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.25 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.71 0.09 library hold time
0.09 data required time
-----------------------------------------------------------------------------
0.09 data required time
-5.25 data arrival time
-----------------------------------------------------------------------------
5.16 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.63 2.06 2.61 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.27 net3 (net)
2.65 0.10 2.71 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.33 0.53 3.25 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _046_ (net)
0.33 0.00 3.25 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.31 1.95 5.20 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _014_ (net)
3.32 0.09 5.29 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.29 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.73 0.07 library hold time
0.07 data required time
-----------------------------------------------------------------------------
0.07 data required time
-5.29 data arrival time
-----------------------------------------------------------------------------
5.22 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.66 2.08 2.63 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
2.67 0.10 2.73 v _102_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.50 1.07 3.80 v _102_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 _050_ (net)
0.50 0.00 3.80 v _103_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.39 3.03 6.83 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _016_ (net)
5.39 0.07 6.89 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.89 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
0.59 1.39 library hold time
1.39 data required time
-----------------------------------------------------------------------------
1.39 data required time
-6.89 data arrival time
-----------------------------------------------------------------------------
5.50 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.01 1.72 2.27 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
2.02 0.07 2.35 v _087_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
0.77 0.78 3.12 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
2 0.01 _041_ (net)
0.77 0.00 3.12 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.69 0.57 3.69 ^ _090_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.02 _043_ (net)
0.69 0.00 3.69 ^ _091_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.37 2.07 5.77 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _011_ (net)
3.38 0.09 5.85 v _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.85 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.03 0.82 clock reconvergence pessimism
-0.75 0.07 library hold time
0.07 data required time
-----------------------------------------------------------------------------
0.07 data required time
-5.85 data arrival time
-----------------------------------------------------------------------------
5.78 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.70 1.56 2.11 v _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net15 (net)
1.70 0.05 2.15 v _080_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.48 0.72 2.87 ^ _080_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.01 _037_ (net)
0.48 0.00 2.87 ^ _081_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.67 2.76 5.63 v _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
4.69 0.13 5.76 v _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.76 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
-1.04 -0.25 library hold time
-0.25 data required time
-----------------------------------------------------------------------------
-0.25 data required time
-5.76 data arrival time
-----------------------------------------------------------------------------
6.01 slack (MET)
Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.44 2.49 3.04 v _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.36 net17 (net)
3.46 0.14 3.18 v fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.75 1.37 4.55 v fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net24 (net)
0.75 0.00 4.55 v _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.40 0.41 4.96 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _039_ (net)
0.40 0.00 4.96 ^ _085_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.31 1.35 6.32 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.33 _009_ (net)
2.34 0.13 6.45 v _121_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.45 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.50 0.30 library hold time
0.30 data required time
-----------------------------------------------------------------------------
0.30 data required time
-6.45 data arrival time
-----------------------------------------------------------------------------
6.15 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.61 3.10 3.66 ^ _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
4.62 0.12 3.77 ^ _092_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.84 0.50 4.27 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _044_ (net)
0.84 0.00 4.27 ^ _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.29 2.04 6.32 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _012_ (net)
3.30 0.09 6.41 v _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.41 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.86 clock uncertainty
-0.06 0.80 clock reconvergence pessimism
-0.73 0.07 library hold time
0.07 data required time
-----------------------------------------------------------------------------
0.07 data required time
-6.41 data arrival time
-----------------------------------------------------------------------------
6.33 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.64 2.59 3.13 v _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
3.66 0.16 3.30 v _082_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.58 1.29 4.58 v _082_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _038_ (net)
0.58 0.00 4.58 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.46 3.08 7.67 ^ _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _008_ (net)
5.46 0.06 7.73 ^ _120_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.73 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
0.60 1.39 library hold time
1.39 data required time
-----------------------------------------------------------------------------
1.39 data required time
-7.73 data arrival time
-----------------------------------------------------------------------------
6.34 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.80 2.68 3.22 v _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
3.83 0.17 3.39 v _072_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.54 1.29 4.68 v _072_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 _032_ (net)
0.54 0.00 4.68 v _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.73 4.29 8.98 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.26 _004_ (net)
7.73 0.10 9.08 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.08 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.85 clock uncertainty
-0.06 0.79 clock reconvergence pessimism
0.89 1.69 library hold time
1.69 data required time
-----------------------------------------------------------------------------
1.69 data required time
-9.08 data arrival time
-----------------------------------------------------------------------------
7.39 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.70 1.56 2.11 v _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net15 (net)
1.70 0.05 2.15 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.38 0.68 2.84 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[3] (net)
0.38 0.00 2.84 v io_out[3] (out)
2.84 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.84 data arrival time
-----------------------------------------------------------------------------
15.59 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.71 1.56 2.11 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
1.71 0.05 2.16 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.38 0.69 2.85 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[11] (net)
0.38 0.00 2.85 v io_out[11] (out)
2.85 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.85 data arrival time
-----------------------------------------------------------------------------
15.60 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.72 1.56 2.10 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
1.73 0.06 2.16 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.38 0.69 2.85 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[9] (net)
0.38 0.00 2.85 v io_out[9] (out)
2.85 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.85 data arrival time
-----------------------------------------------------------------------------
15.60 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.80 1.61 2.15 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
1.81 0.06 2.22 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.38 0.70 2.92 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[15] (net)
0.38 0.00 2.92 v io_out[15] (out)
2.92 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.92 data arrival time
-----------------------------------------------------------------------------
15.67 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.01 1.72 2.27 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
2.02 0.07 2.35 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.38 0.72 3.07 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[6] (net)
0.38 0.00 3.07 v io_out[6] (out)
3.07 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.07 data arrival time
-----------------------------------------------------------------------------
15.82 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.07 1.75 2.30 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
2.08 0.08 2.38 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.73 3.11 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[16] (net)
0.39 0.00 3.12 v io_out[16] (out)
3.12 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.12 data arrival time
-----------------------------------------------------------------------------
15.87 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.17 1.81 2.36 v _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net12 (net)
2.18 0.09 2.44 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.74 3.19 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[19] (net)
0.39 0.00 3.19 v io_out[19] (out)
3.19 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.19 data arrival time
-----------------------------------------------------------------------------
15.94 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.20 1.82 2.36 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
2.21 0.08 2.45 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.75 3.20 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[13] (net)
0.39 0.00 3.20 v io_out[13] (out)
3.20 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.20 data arrival time
-----------------------------------------------------------------------------
15.95 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.26 1.85 2.39 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.24 net10 (net)
2.28 0.09 2.49 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.75 3.24 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[17] (net)
0.39 0.00 3.24 v io_out[17] (out)
3.24 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.24 data arrival time
-----------------------------------------------------------------------------
15.99 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.63 2.06 2.61 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.27 net3 (net)
2.65 0.10 2.71 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.79 3.51 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[10] (net)
0.40 0.00 3.51 v io_out[10] (out)
3.51 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.51 data arrival time
-----------------------------------------------------------------------------
16.26 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.66 2.08 2.63 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
2.67 0.10 2.73 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.80 3.53 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[12] (net)
0.40 0.00 3.53 v io_out[12] (out)
3.53 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.53 data arrival time
-----------------------------------------------------------------------------
16.28 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.77 2.12 2.67 v _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
2.78 0.11 2.79 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.81 3.60 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[8] (net)
0.40 0.00 3.60 v io_out[8] (out)
3.60 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.60 data arrival time
-----------------------------------------------------------------------------
16.35 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.78 2.14 2.69 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
2.80 0.11 2.80 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.81 3.61 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[14] (net)
0.40 0.00 3.61 v io_out[14] (out)
3.61 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.61 data arrival time
-----------------------------------------------------------------------------
16.36 slack (MET)
Startpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.81 2.14 2.69 v _123_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.29 net19 (net)
2.83 0.12 2.81 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.81 3.62 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[7] (net)
0.40 0.00 3.62 v io_out[7] (out)
3.62 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.62 data arrival time
-----------------------------------------------------------------------------
16.37 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.93 2.22 2.76 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
2.95 0.12 2.88 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.41 0.82 3.71 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[18] (net)
0.41 0.00 3.71 v io_out[18] (out)
3.71 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.71 data arrival time
-----------------------------------------------------------------------------
16.46 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.01 2.26 2.81 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
3.03 0.13 2.94 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.41 0.83 3.77 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[2] (net)
0.41 0.00 3.77 v io_out[2] (out)
3.77 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.77 data arrival time
-----------------------------------------------------------------------------
16.52 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.95 1.68 2.23 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
1.96 0.07 2.30 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.76 1.10 3.41 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net25 (net)
0.76 0.00 3.41 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.35 0.54 3.95 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[1] (net)
0.35 0.00 3.95 v io_out[1] (out)
3.95 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.95 data arrival time
-----------------------------------------------------------------------------
16.70 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.64 2.59 3.13 v _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
3.67 0.16 3.30 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.42 0.89 4.19 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[4] (net)
0.42 0.00 4.19 v io_out[4] (out)
4.19 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.19 data arrival time
-----------------------------------------------------------------------------
16.94 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 0.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.54 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.80 2.68 3.22 v _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
3.83 0.17 3.39 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.43 0.90 4.30 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[0] (net)
0.43 0.00 4.30 v io_out[0] (out)
4.30 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.30 data arrival time
-----------------------------------------------------------------------------
17.05 slack (MET)
Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.55 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.44 2.49 3.04 v _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.36 net17 (net)
3.46 0.14 3.18 v fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.75 1.37 4.55 v fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net24 (net)
0.75 0.00 4.56 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.35 0.54 5.10 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[5] (net)
0.35 0.00 5.10 v io_out[5] (out)
5.10 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-5.10 data arrival time
-----------------------------------------------------------------------------
17.85 slack (MET)
======================= Fastest Corner ===================================
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.90 1.41 1.77 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
1.91 0.06 1.83 ^ fanout23/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.46 0.33 2.16 ^ fanout23/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net23 (net)
0.46 0.00 2.16 ^ _095_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
0.89 0.55 2.71 v _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.19 _013_ (net)
0.90 0.07 2.78 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.78 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
-0.16 0.44 library hold time
0.44 data required time
-----------------------------------------------------------------------------
0.44 data required time
-2.78 data arrival time
-----------------------------------------------------------------------------
2.34 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.21 1.04 1.40 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
1.22 0.06 1.46 v _110_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.23 0.44 1.89 ^ _110_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _055_ (net)
0.23 0.00 1.89 ^ _111_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.28 0.80 2.69 v _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
1.28 0.04 2.73 v _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.73 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
-0.25 0.35 library hold time
0.35 data required time
-----------------------------------------------------------------------------
0.35 data required time
-2.73 data arrival time
-----------------------------------------------------------------------------
2.38 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.39 1.13 1.48 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net9 (net)
1.41 0.08 1.56 v _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.33 0.64 2.20 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 _020_ (net)
0.33 0.00 2.20 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.18 0.91 3.11 ^ _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _001_ (net)
1.19 0.05 3.16 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.16 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.02 0.62 clock reconvergence pessimism
0.10 0.72 library hold time
0.72 data required time
-----------------------------------------------------------------------------
0.72 data required time
-3.16 data arrival time
-----------------------------------------------------------------------------
2.44 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.48 1.18 1.53 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
1.49 0.08 1.61 v fanout22/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.30 0.63 2.24 v fanout22/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 net22 (net)
0.30 0.00 2.24 v _105_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.17 0.91 3.15 ^ _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _017_ (net)
1.18 0.05 3.21 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.21 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
0.10 0.70 library hold time
0.70 data required time
-----------------------------------------------------------------------------
0.70 data required time
-3.21 data arrival time
-----------------------------------------------------------------------------
2.51 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.31 1.09 1.44 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
1.32 0.07 1.51 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.51 0.73 2.24 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net25 (net)
0.51 0.00 2.25 v _074_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.25 0.25 2.49 ^ _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _033_ (net)
0.25 0.00 2.49 ^ _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
0.81 0.50 2.99 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.17 _005_ (net)
0.82 0.06 3.05 v _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.05 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.14 0.46 library hold time
0.46 data required time
-----------------------------------------------------------------------------
0.46 data required time
-3.05 data arrival time
-----------------------------------------------------------------------------
2.58 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.15 1.01 1.36 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
1.16 0.05 1.42 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.21 0.41 1.83 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _049_ (net)
0.21 0.00 1.83 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.78 1.06 2.89 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.20 _015_ (net)
1.78 0.07 2.96 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.96 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
-0.37 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-2.96 data arrival time
-----------------------------------------------------------------------------
2.73 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.87 1.39 1.74 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
1.89 0.11 1.85 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.29 0.44 2.29 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _052_ (net)
0.29 0.00 2.29 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.35 0.84 3.14 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.15 _018_ (net)
1.35 0.04 3.17 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.17 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
-0.27 0.33 library hold time
0.33 data required time
-----------------------------------------------------------------------------
0.33 data required time
-3.17 data arrival time
-----------------------------------------------------------------------------
2.84 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.31 1.09 1.44 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
1.32 0.07 1.51 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
0.55 0.52 2.03 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
2 0.02 _035_ (net)
0.55 0.00 2.03 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.14 0.07 2.11 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _036_ (net)
0.14 0.00 2.11 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.95 1.64 3.75 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _006_ (net)
2.95 0.05 3.80 ^ _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.80 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
0.34 0.94 library hold time
0.94 data required time
-----------------------------------------------------------------------------
0.94 data required time
-3.80 data arrival time
-----------------------------------------------------------------------------
2.86 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.97 1.43 1.79 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
2.00 0.12 1.91 v _064_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.22 0.40 2.30 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _026_ (net)
0.22 0.00 2.30 ^ _068_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.57 0.94 3.24 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.17 _002_ (net)
1.57 0.06 3.30 v _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.30 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
-0.32 0.28 library hold time
0.28 data required time
-----------------------------------------------------------------------------
0.28 data required time
-3.30 data arrival time
-----------------------------------------------------------------------------
3.02 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.39 1.13 1.48 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net9 (net)
1.41 0.08 1.56 v _056_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.33 0.64 2.20 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 _020_ (net)
0.33 0.00 2.20 v _060_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.30 1.85 4.05 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _000_ (net)
3.30 0.06 4.11 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.11 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
0.39 0.99 library hold time
0.99 data required time
-----------------------------------------------------------------------------
0.99 data required time
-4.11 data arrival time
-----------------------------------------------------------------------------
3.12 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.35 1.11 1.47 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
1.36 0.07 1.54 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.22 0.32 1.86 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _040_ (net)
0.22 0.00 1.86 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.36 1.37 3.23 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.27 _010_ (net)
2.38 0.10 3.33 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.33 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.50 0.10 library hold time
0.10 data required time
-----------------------------------------------------------------------------
0.10 data required time
-3.33 data arrival time
-----------------------------------------------------------------------------
3.23 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.46 1.17 1.52 v _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.22 net12 (net)
1.47 0.08 1.60 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.26 0.52 2.12 ^ _070_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
0.26 0.00 2.12 ^ _071_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.12 1.27 3.39 v _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.24 _003_ (net)
2.13 0.08 3.47 v _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.47 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.45 0.15 library hold time
0.15 data required time
-----------------------------------------------------------------------------
0.15 data required time
-3.47 data arrival time
-----------------------------------------------------------------------------
3.32 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.77 1.33 1.69 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.27 net3 (net)
1.79 0.10 1.79 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.20 0.35 2.14 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _046_ (net)
0.20 0.00 2.14 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.18 1.27 3.41 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _014_ (net)
2.20 0.09 3.50 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.50 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.47 0.14 library hold time
0.14 data required time
-----------------------------------------------------------------------------
0.14 data required time
-3.50 data arrival time
-----------------------------------------------------------------------------
3.36 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.79 1.34 1.70 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
1.81 0.10 1.80 v _102_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.33 0.71 2.51 v _102_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 _050_ (net)
0.33 0.00 2.51 v _103_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.36 1.88 4.39 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _016_ (net)
3.37 0.07 4.46 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.46 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
0.39 1.00 library hold time
1.00 data required time
-----------------------------------------------------------------------------
1.00 data required time
-4.46 data arrival time
-----------------------------------------------------------------------------
3.46 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.35 1.11 1.47 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
1.36 0.07 1.54 v _087_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
0.53 0.52 2.07 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
2 0.01 _041_ (net)
0.53 0.00 2.07 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.23 0.17 2.23 v _090_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.02 _043_ (net)
0.23 0.00 2.23 v _091_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.56 2.50 4.74 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _011_ (net)
4.57 0.09 4.83 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.83 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.02 0.62 clock reconvergence pessimism
0.56 1.18 library hold time
1.18 data required time
-----------------------------------------------------------------------------
1.18 data required time
-4.83 data arrival time
-----------------------------------------------------------------------------
3.65 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.14 1.01 1.37 v _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
1.15 0.05 1.41 v _080_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.29 0.47 1.88 ^ _080_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.01 _037_ (net)
0.29 0.00 1.88 ^ _081_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.08 1.79 3.67 v _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
3.10 0.13 3.81 v _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.81 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
-0.66 -0.06 library hold time
-0.06 data required time
-----------------------------------------------------------------------------
-0.06 data required time
-3.81 data arrival time
-----------------------------------------------------------------------------
3.87 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.03 2.53 2.88 ^ _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
4.05 0.16 3.05 ^ _082_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.58 0.27 3.32 ^ _082_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _038_ (net)
0.58 0.00 3.32 ^ _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.20 0.13 3.46 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _039_ (net)
0.20 0.00 3.46 v _085_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.33 1.25 4.71 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.33 _009_ (net)
2.36 0.13 4.84 ^ _121_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.84 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.02 0.62 clock reconvergence pessimism
0.25 0.87 library hold time
0.87 data required time
-----------------------------------------------------------------------------
0.87 data required time
-4.84 data arrival time
-----------------------------------------------------------------------------
3.97 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.86 1.37 1.73 v _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
1.89 0.11 1.84 v _092_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.35 0.74 2.58 v _092_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _044_ (net)
0.35 0.00 2.58 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.49 2.48 5.06 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _012_ (net)
4.50 0.09 5.16 ^ _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.16 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
0.55 1.16 library hold time
1.16 data required time
-----------------------------------------------------------------------------
1.16 data required time
-5.16 data arrival time
-----------------------------------------------------------------------------
4.00 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.45 1.67 2.02 v _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
2.49 0.16 2.18 v _082_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.38 0.86 3.05 v _082_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.05 _038_ (net)
0.38 0.00 3.05 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.40 1.92 4.97 ^ _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _008_ (net)
3.41 0.06 5.03 ^ _120_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.03 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
0.40 1.00 library hold time
1.00 data required time
-----------------------------------------------------------------------------
1.00 data required time
-5.03 data arrival time
-----------------------------------------------------------------------------
4.03 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.56 1.73 2.08 v _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
2.60 0.17 2.25 v _072_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.36 0.86 3.12 v _072_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.04 _032_ (net)
0.36 0.00 3.12 v _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.82 2.66 5.78 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.26 _004_ (net)
4.83 0.10 5.88 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.88 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.04 0.60 clock reconvergence pessimism
0.60 1.20 library hold time
1.20 data required time
-----------------------------------------------------------------------------
1.20 data required time
-5.88 data arrival time
-----------------------------------------------------------------------------
4.68 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.14 1.01 1.37 v _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
1.15 0.05 1.41 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.24 0.44 1.85 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[3] (net)
0.24 0.00 1.85 v io_out[3] (out)
1.85 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.85 data arrival time
-----------------------------------------------------------------------------
14.60 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.15 1.01 1.36 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
1.16 0.05 1.42 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.44 1.86 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[11] (net)
0.25 0.00 1.86 v io_out[11] (out)
1.86 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.86 data arrival time
-----------------------------------------------------------------------------
14.61 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.16 1.01 1.36 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
1.17 0.06 1.42 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.44 1.86 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[9] (net)
0.25 0.00 1.86 v io_out[9] (out)
1.86 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.86 data arrival time
-----------------------------------------------------------------------------
14.61 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.21 1.04 1.40 v _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
1.22 0.06 1.46 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.45 1.90 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[15] (net)
0.25 0.00 1.91 v io_out[15] (out)
1.91 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.91 data arrival time
-----------------------------------------------------------------------------
14.66 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.35 1.11 1.47 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
1.36 0.07 1.54 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.46 2.01 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[6] (net)
0.25 0.00 2.01 v io_out[6] (out)
2.01 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.01 data arrival time
-----------------------------------------------------------------------------
14.76 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.39 1.13 1.48 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net9 (net)
1.41 0.08 1.57 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.47 2.03 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[16] (net)
0.25 0.00 2.04 v io_out[16] (out)
2.04 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.04 data arrival time
-----------------------------------------------------------------------------
14.79 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.46 1.17 1.52 v _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.22 net12 (net)
1.47 0.08 1.61 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.48 2.08 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[19] (net)
0.25 0.00 2.09 v io_out[19] (out)
2.09 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.09 data arrival time
-----------------------------------------------------------------------------
14.84 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.48 1.18 1.53 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
1.49 0.08 1.61 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.48 2.09 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[13] (net)
0.25 0.00 2.09 v io_out[13] (out)
2.09 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.09 data arrival time
-----------------------------------------------------------------------------
14.84 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.52 1.19 1.55 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.24 net10 (net)
1.54 0.09 1.64 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.48 2.12 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[17] (net)
0.26 0.00 2.12 v io_out[17] (out)
2.12 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.12 data arrival time
-----------------------------------------------------------------------------
14.87 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.77 1.33 1.69 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.27 net3 (net)
1.79 0.10 1.79 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.51 2.30 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[10] (net)
0.26 0.00 2.30 v io_out[10] (out)
2.30 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.30 data arrival time
-----------------------------------------------------------------------------
15.05 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.79 1.34 1.70 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
1.81 0.10 1.80 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.51 2.31 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[12] (net)
0.26 0.00 2.31 v io_out[12] (out)
2.31 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.31 data arrival time
-----------------------------------------------------------------------------
15.06 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.86 1.37 1.73 v _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
1.89 0.11 1.84 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.52 2.36 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[8] (net)
0.26 0.00 2.36 v io_out[8] (out)
2.36 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.36 data arrival time
-----------------------------------------------------------------------------
15.11 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.87 1.39 1.74 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
1.90 0.11 1.85 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.52 2.37 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[14] (net)
0.26 0.00 2.37 v io_out[14] (out)
2.37 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.37 data arrival time
-----------------------------------------------------------------------------
15.12 slack (MET)
Startpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.89 1.38 1.74 v _123_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.29 net19 (net)
1.92 0.12 1.85 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.52 2.37 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[7] (net)
0.26 0.00 2.37 v io_out[7] (out)
2.37 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.37 data arrival time
-----------------------------------------------------------------------------
15.12 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.97 1.43 1.79 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
2.00 0.12 1.91 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.27 0.53 2.43 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[18] (net)
0.27 0.00 2.44 v io_out[18] (out)
2.44 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.44 data arrival time
-----------------------------------------------------------------------------
15.19 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.03 1.46 1.81 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
2.05 0.13 1.94 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.27 0.53 2.47 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[2] (net)
0.27 0.00 2.47 v io_out[2] (out)
2.47 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.47 data arrival time
-----------------------------------------------------------------------------
15.22 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.31 1.09 1.44 v _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
1.32 0.07 1.51 v fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.51 0.73 2.24 v fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net25 (net)
0.51 0.00 2.25 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.23 0.35 2.60 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[1] (net)
0.23 0.00 2.60 v io_out[1] (out)
2.60 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.60 data arrival time
-----------------------------------------------------------------------------
15.35 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.45 1.67 2.02 v _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
2.49 0.16 2.19 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.57 2.75 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[4] (net)
0.28 0.00 2.75 v io_out[4] (out)
2.75 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.75 data arrival time
-----------------------------------------------------------------------------
15.50 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.35 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.56 1.73 2.08 v _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
2.60 0.17 2.25 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.57 2.83 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[0] (net)
0.28 0.00 2.83 v io_out[0] (out)
2.83 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.83 data arrival time
-----------------------------------------------------------------------------
15.58 slack (MET)
Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.32 1.61 1.97 v _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.36 net17 (net)
2.35 0.14 2.11 v fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.50 0.91 3.02 v fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net24 (net)
0.50 0.00 3.03 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.23 0.35 3.37 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[5] (net)
0.23 0.00 3.37 v io_out[5] (out)
3.37 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.37 data arrival time
-----------------------------------------------------------------------------
16.12 slack (MET)
min_report_end
max_report
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
======================= Slowest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.71 0.88 19.26 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.71 0.00 19.26 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
18.30 11.18 30.43 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
18.30 0.15 30.58 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
30.58 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
0.87 66.59 library setup time
66.59 data required time
-----------------------------------------------------------------------------
66.59 data required time
-30.58 data arrival time
-----------------------------------------------------------------------------
36.01 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.60 0.81 19.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.60 0.00 19.19 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
13.94 8.56 27.76 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.26 _004_ (net)
13.94 0.11 27.87 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
27.87 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
0.46 66.18 library setup time
66.18 data required time
-----------------------------------------------------------------------------
66.18 data required time
-27.87 data arrival time
-----------------------------------------------------------------------------
38.31 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.98 1.00 18.64 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.98 0.00 18.64 ^ _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.50 0.31 18.95 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _042_ (net)
0.50 0.00 18.95 v _089_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
14.00 8.59 27.54 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.27 _010_ (net)
14.00 0.11 27.65 ^ _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
27.65 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
0.47 66.20 library setup time
66.20 data required time
-----------------------------------------------------------------------------
66.20 data required time
-27.65 data arrival time
-----------------------------------------------------------------------------
38.55 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.71 0.88 19.26 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.71 0.00 19.26 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
13.22 8.13 27.39 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _011_ (net)
13.22 0.10 27.49 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
27.49 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
0.40 66.11 library setup time
66.11 data required time
-----------------------------------------------------------------------------
66.11 data required time
-27.49 data arrival time
-----------------------------------------------------------------------------
38.63 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.60 0.81 19.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.60 0.00 19.19 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
12.98 7.99 27.18 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _012_ (net)
12.99 0.10 27.28 ^ _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
27.28 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
0.37 66.11 library setup time
66.11 data required time
-----------------------------------------------------------------------------
66.11 data required time
-27.28 data arrival time
-----------------------------------------------------------------------------
38.82 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.71 0.88 19.26 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.71 0.00 19.26 v _071_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
12.62 7.77 27.02 ^ _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.24 _003_ (net)
12.62 0.09 27.12 ^ _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
27.12 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
0.34 66.07 library setup time
66.07 data required time
-----------------------------------------------------------------------------
66.07 data required time
-27.12 data arrival time
-----------------------------------------------------------------------------
38.96 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.98 1.00 18.64 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.98 0.00 18.64 ^ _098_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.45 0.28 18.92 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _048_ (net)
0.45 0.00 18.92 v _099_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
12.95 7.95 26.87 ^ _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _014_ (net)
12.96 0.10 26.98 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
26.98 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
0.37 66.10 library setup time
66.10 data required time
-----------------------------------------------------------------------------
66.10 data required time
-26.98 data arrival time
-----------------------------------------------------------------------------
39.13 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.71 0.88 19.26 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.71 0.00 19.26 v _103_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.75 6.04 25.30 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _016_ (net)
9.75 0.07 25.37 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
25.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
0.07 65.81 library setup time
65.81 data required time
-----------------------------------------------------------------------------
65.81 data required time
-25.37 data arrival time
-----------------------------------------------------------------------------
40.43 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.60 0.81 19.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.60 0.00 19.19 v _083_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.86 6.10 25.29 ^ _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _008_ (net)
9.87 0.07 25.36 ^ _120_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
25.36 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
0.08 65.80 library setup time
65.80 data required time
-----------------------------------------------------------------------------
65.80 data required time
-25.36 data arrival time
-----------------------------------------------------------------------------
40.44 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.60 0.81 19.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.60 0.00 19.19 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.57 5.92 25.11 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _000_ (net)
9.57 0.07 25.18 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
25.18 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
0.06 65.79 library setup time
65.79 data required time
-----------------------------------------------------------------------------
65.79 data required time
-25.18 data arrival time
-----------------------------------------------------------------------------
40.61 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
10.58 6.57 24.95 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.20 _015_ (net)
10.58 0.07 25.02 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
25.02 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
0.15 65.87 library setup time
65.87 data required time
-----------------------------------------------------------------------------
65.87 data required time
-25.02 data arrival time
-----------------------------------------------------------------------------
40.85 slack (MET)
Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.77 7.13 8.21 ^ _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.36 net17 (net)
9.77 0.16 8.37 ^ fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.09 1.34 9.71 ^ fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net24 (net)
2.09 0.00 9.72 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.61 1.08 10.80 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[5] (net)
0.61 0.00 10.80 ^ io_out[5] (out)
10.80 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-10.80 data arrival time
-----------------------------------------------------------------------------
40.95 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.98 1.00 18.64 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.98 0.00 18.64 ^ _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.53 0.30 18.94 v _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _029_ (net)
0.53 0.00 18.94 v _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.31 5.76 24.71 ^ _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.17 _002_ (net)
9.31 0.06 24.77 ^ _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
24.77 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
0.03 65.75 library setup time
65.75 data required time
-----------------------------------------------------------------------------
65.75 data required time
-24.77 data arrival time
-----------------------------------------------------------------------------
40.98 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
10.79 7.73 8.80 ^ _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
10.80 0.19 8.99 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.78 1.63 10.62 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[0] (net)
0.78 0.00 10.62 ^ io_out[0] (out)
10.62 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-10.62 data arrival time
-----------------------------------------------------------------------------
41.13 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.98 1.00 18.64 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.98 0.00 18.64 ^ _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.53 0.30 18.94 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _036_ (net)
0.53 0.00 18.94 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
8.57 5.32 24.26 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _006_ (net)
8.57 0.06 24.32 ^ _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
24.32 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
-0.04 65.70 library setup time
65.70 data required time
-----------------------------------------------------------------------------
65.70 data required time
-24.32 data arrival time
-----------------------------------------------------------------------------
41.38 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
10.34 7.45 8.53 ^ _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
10.35 0.18 8.71 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.77 1.61 10.32 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[4] (net)
0.77 0.00 10.32 ^ io_out[4] (out)
10.32 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-10.32 data arrival time
-----------------------------------------------------------------------------
41.43 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.20 1.35 17.73 ^ _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
1.20 0.00 17.73 ^ _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.83 0.49 18.22 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _039_ (net)
0.83 0.00 18.22 v _085_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
9.07 5.67 23.90 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.33 _009_ (net)
9.08 0.15 24.04 ^ _121_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
24.04 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
0.01 65.74 library setup time
65.74 data required time
-----------------------------------------------------------------------------
65.74 data required time
-24.04 data arrival time
-----------------------------------------------------------------------------
41.70 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.20 1.35 17.73 ^ _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
1.20 0.00 17.73 ^ _108_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.64 0.48 18.21 v _108_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _054_ (net)
0.64 0.00 18.21 v _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
8.03 5.02 23.23 ^ _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.15 _018_ (net)
8.03 0.04 23.27 ^ _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
23.27 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
-0.09 65.63 library setup time
65.63 data required time
-----------------------------------------------------------------------------
65.63 data required time
-23.27 data arrival time
-----------------------------------------------------------------------------
42.36 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _111_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.59 4.80 23.18 ^ _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
7.60 0.04 23.22 ^ _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
23.22 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
-0.13 65.59 library setup time
65.59 data required time
-----------------------------------------------------------------------------
65.59 data required time
-23.22 data arrival time
-----------------------------------------------------------------------------
42.37 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.56 6.41 7.50 ^ _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
8.56 0.14 7.64 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.74 1.52 9.16 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[2] (net)
0.74 0.00 9.16 ^ io_out[2] (out)
9.16 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-9.16 data arrival time
-----------------------------------------------------------------------------
42.59 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.34 6.28 7.35 ^ _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
8.34 0.14 7.49 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.74 1.51 8.99 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[18] (net)
0.74 0.00 8.99 ^ io_out[18] (out)
8.99 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-8.99 data arrival time
-----------------------------------------------------------------------------
42.76 slack (MET)
Startpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.99 6.07 7.14 ^ _123_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.29 net19 (net)
7.99 0.13 7.27 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.73 1.48 8.75 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[7] (net)
0.73 0.00 8.75 ^ io_out[7] (out)
8.75 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-8.75 data arrival time
-----------------------------------------------------------------------------
43.00 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.92 6.03 7.10 ^ _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
7.92 0.13 7.23 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.73 1.48 8.71 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[14] (net)
0.73 0.00 8.71 ^ io_out[14] (out)
8.71 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-8.71 data arrival time
-----------------------------------------------------------------------------
43.04 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.87 6.00 7.09 ^ _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
7.88 0.13 7.22 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.73 1.48 8.70 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[8] (net)
0.73 0.00 8.70 ^ io_out[8] (out)
8.70 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-8.70 data arrival time
-----------------------------------------------------------------------------
43.05 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.54 4.62 5.71 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
5.55 0.08 5.79 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.18 1.62 7.41 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.08 net25 (net)
2.18 0.01 7.42 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.61 1.09 8.50 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[1] (net)
0.61 0.00 8.51 ^ io_out[1] (out)
8.51 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-8.51 data arrival time
-----------------------------------------------------------------------------
43.24 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.56 5.83 6.91 ^ _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
7.57 0.12 7.03 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.72 1.47 8.49 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[12] (net)
0.72 0.00 8.50 ^ io_out[12] (out)
8.50 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-8.50 data arrival time
-----------------------------------------------------------------------------
43.25 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
7.50 5.79 6.87 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net3 (net)
7.50 0.11 6.99 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.72 1.46 8.45 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[10] (net)
0.72 0.00 8.45 ^ io_out[10] (out)
8.45 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-8.45 data arrival time
-----------------------------------------------------------------------------
43.30 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _094_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.67 0.51 18.15 v _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _045_ (net)
0.67 0.00 18.15 v _095_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
5.28 3.40 21.55 ^ _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.19 _013_ (net)
5.28 0.08 21.62 ^ _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.62 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
-0.35 65.37 library setup time
65.37 data required time
-----------------------------------------------------------------------------
65.37 data required time
-21.62 data arrival time
-----------------------------------------------------------------------------
43.74 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.20 1.35 17.73 ^ _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
1.20 0.00 17.73 ^ _074_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.82 0.46 18.19 v _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _033_ (net)
0.82 0.00 18.19 v _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
4.81 3.15 21.34 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.17 _005_ (net)
4.81 0.06 21.40 ^ _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.40 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.43 65.98 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 65.98 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.73 clock uncertainty
0.00 65.73 clock reconvergence pessimism
-0.38 65.35 library setup time
65.35 data required time
-----------------------------------------------------------------------------
65.35 data required time
-21.40 data arrival time
-----------------------------------------------------------------------------
43.95 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.44 5.15 6.22 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.24 net10 (net)
6.45 0.10 6.32 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.70 1.41 7.73 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[17] (net)
0.70 0.00 7.73 ^ io_out[17] (out)
7.73 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-7.73 data arrival time
-----------------------------------------------------------------------------
44.02 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.20 1.35 17.73 ^ _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
1.20 0.00 17.73 ^ _062_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.65 0.49 18.21 v _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _025_ (net)
0.65 0.00 18.21 v _063_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
4.59 3.00 21.22 ^ _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _001_ (net)
4.59 0.05 21.27 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.27 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
-0.41 65.31 library setup time
65.31 data required time
-----------------------------------------------------------------------------
65.31 data required time
-21.27 data arrival time
-----------------------------------------------------------------------------
44.04 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.26 5.05 6.12 ^ _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
6.26 0.09 6.21 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.70 1.40 7.61 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[13] (net)
0.70 0.00 7.61 ^ io_out[13] (out)
7.61 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-7.61 data arrival time
-----------------------------------------------------------------------------
44.14 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _104_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.63 0.47 18.11 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _051_ (net)
0.63 0.00 18.11 v _105_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
4.60 3.00 21.11 ^ _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _017_ (net)
4.60 0.06 21.17 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.17 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
-0.41 65.31 library setup time
65.31 data required time
-----------------------------------------------------------------------------
65.31 data required time
-21.17 data arrival time
-----------------------------------------------------------------------------
44.14 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.17 5.00 6.09 ^ _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net12 (net)
6.18 0.10 6.18 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.70 1.39 7.57 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[19] (net)
0.70 0.00 7.58 ^ io_out[19] (out)
7.58 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-7.58 data arrival time
-----------------------------------------------------------------------------
44.17 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.90 4.84 5.92 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
5.91 0.09 6.02 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.69 1.38 7.39 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[16] (net)
0.69 0.00 7.40 ^ io_out[16] (out)
7.40 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-7.40 data arrival time
-----------------------------------------------------------------------------
44.35 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.21 0.47 1.09 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.21 0.00 1.09 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.73 4.74 5.82 ^ _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
5.73 0.08 5.91 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.68 1.37 7.27 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[6] (net)
0.68 0.00 7.27 ^ io_out[6] (out)
7.27 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-7.27 data arrival time
-----------------------------------------------------------------------------
44.48 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.14 4.39 5.46 ^ _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
5.14 0.07 5.53 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.68 1.34 6.86 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[15] (net)
0.68 0.00 6.86 ^ io_out[15] (out)
6.86 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.86 data arrival time
-----------------------------------------------------------------------------
44.89 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.90 4.24 5.31 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
4.90 0.07 5.38 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.67 1.32 6.70 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[9] (net)
0.67 0.00 6.70 ^ io_out[9] (out)
6.70 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.70 data arrival time
-----------------------------------------------------------------------------
45.05 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.87 4.23 5.30 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
4.87 0.06 5.36 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.67 1.32 6.68 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[11] (net)
0.67 0.00 6.68 ^ io_out[11] (out)
6.68 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.68 data arrival time
-----------------------------------------------------------------------------
45.07 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.27 0.13 0.13 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 0.13 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.48 0.61 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 0.61 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.46 1.07 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 1.07 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.84 4.22 5.29 ^ _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net15 (net)
4.84 0.05 5.34 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.66 1.31 6.65 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[3] (net)
0.66 0.00 6.65 ^ io_out[3] (out)
6.65 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.65 data arrival time
-----------------------------------------------------------------------------
45.10 slack (MET)
======================= Typical Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.40 0.00 16.63 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
10.13 6.14 22.77 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
10.13 0.15 22.92 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
22.92 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.70 65.99 library setup time
65.99 data required time
-----------------------------------------------------------------------------
65.99 data required time
-22.92 data arrival time
-----------------------------------------------------------------------------
43.07 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.34 0.00 16.59 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.73 4.70 21.29 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.26 _004_ (net)
7.73 0.11 21.40 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.40 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.43 65.72 library setup time
65.72 data required time
-----------------------------------------------------------------------------
65.72 data required time
-21.40 data arrival time
-----------------------------------------------------------------------------
44.32 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.56 0.56 16.29 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.56 0.00 16.29 ^ _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.30 0.16 16.45 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _042_ (net)
0.30 0.00 16.45 v _089_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.76 4.71 21.17 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.27 _010_ (net)
7.77 0.11 21.28 ^ _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.28 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.43 65.73 library setup time
65.73 data required time
-----------------------------------------------------------------------------
65.73 data required time
-21.28 data arrival time
-----------------------------------------------------------------------------
44.45 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.40 0.00 16.63 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.31 4.47 21.10 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _011_ (net)
7.32 0.10 21.20 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.20 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.38 65.67 library setup time
65.67 data required time
-----------------------------------------------------------------------------
65.67 data required time
-21.20 data arrival time
-----------------------------------------------------------------------------
44.47 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.34 0.00 16.59 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.20 4.38 20.97 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _012_ (net)
7.20 0.10 21.08 ^ _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.08 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.37 65.67 library setup time
65.67 data required time
-----------------------------------------------------------------------------
65.67 data required time
-21.08 data arrival time
-----------------------------------------------------------------------------
44.59 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.40 0.00 16.63 v _071_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.98 4.28 20.91 ^ _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.24 _003_ (net)
6.98 0.09 21.00 ^ _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.00 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.34 65.64 library setup time
65.64 data required time
-----------------------------------------------------------------------------
65.64 data required time
-21.00 data arrival time
-----------------------------------------------------------------------------
44.65 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.56 0.56 16.29 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.56 0.00 16.29 ^ _098_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.27 0.15 16.43 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _048_ (net)
0.27 0.00 16.43 v _099_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.20 4.37 20.80 ^ _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _014_ (net)
7.20 0.10 20.90 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
20.90 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.37 65.67 library setup time
65.67 data required time
-----------------------------------------------------------------------------
65.67 data required time
-20.90 data arrival time
-----------------------------------------------------------------------------
44.77 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.40 0.00 16.63 v _103_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.39 3.32 19.95 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _016_ (net)
5.39 0.07 20.02 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
20.02 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.16 65.46 library setup time
65.46 data required time
-----------------------------------------------------------------------------
65.46 data required time
-20.02 data arrival time
-----------------------------------------------------------------------------
45.44 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.34 0.00 16.59 v _083_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.46 3.35 19.95 ^ _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _008_ (net)
5.46 0.07 20.01 ^ _120_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
20.01 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.17 65.46 library setup time
65.46 data required time
-----------------------------------------------------------------------------
65.46 data required time
-20.01 data arrival time
-----------------------------------------------------------------------------
45.45 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.34 0.45 16.59 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.34 0.00 16.59 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.29 3.25 19.84 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _000_ (net)
5.29 0.07 19.91 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.91 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.15 65.45 library setup time
65.45 data required time
-----------------------------------------------------------------------------
65.45 data required time
-19.91 data arrival time
-----------------------------------------------------------------------------
45.54 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.32 4.44 5.04 ^ _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
6.34 0.19 5.23 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.45 0.97 6.20 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[0] (net)
0.45 0.00 6.20 ^ io_out[0] (out)
6.20 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.20 data arrival time
-----------------------------------------------------------------------------
45.55 slack (MET)
Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.73 4.09 4.70 ^ _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.36 net17 (net)
5.74 0.16 4.86 ^ fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.21 0.72 5.58 ^ fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net24 (net)
1.21 0.00 5.58 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.35 0.62 6.20 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[5] (net)
0.35 0.00 6.20 ^ io_out[5] (out)
6.20 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.20 data arrival time
-----------------------------------------------------------------------------
45.55 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.84 3.61 19.75 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.20 _015_ (net)
5.85 0.07 19.83 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.83 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.21 65.50 library setup time
65.50 data required time
-----------------------------------------------------------------------------
65.50 data required time
-19.83 data arrival time
-----------------------------------------------------------------------------
45.68 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.05 4.28 4.88 ^ _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
6.07 0.18 5.07 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.45 0.95 6.02 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[4] (net)
0.45 0.00 6.02 ^ io_out[4] (out)
6.02 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.02 data arrival time
-----------------------------------------------------------------------------
45.73 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.56 0.56 16.29 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.56 0.00 16.29 ^ _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.32 0.16 16.45 v _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _029_ (net)
0.32 0.00 16.45 v _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.15 3.17 19.62 ^ _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.17 _002_ (net)
5.16 0.06 19.68 ^ _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.68 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.13 65.43 library setup time
65.43 data required time
-----------------------------------------------------------------------------
65.43 data required time
-19.68 data arrival time
-----------------------------------------------------------------------------
45.75 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.56 0.56 16.29 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.56 0.00 16.29 ^ _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.31 0.16 16.45 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _036_ (net)
0.31 0.00 16.45 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.74 2.93 19.37 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _006_ (net)
4.75 0.06 19.43 ^ _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.43 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.09 65.39 library setup time
65.39 data required time
-----------------------------------------------------------------------------
65.39 data required time
-19.43 data arrival time
-----------------------------------------------------------------------------
45.96 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.69 0.77 15.77 ^ _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.69 0.00 15.77 ^ _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.49 0.27 16.04 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _039_ (net)
0.49 0.00 16.04 v _085_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
5.01 3.08 19.12 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.33 _009_ (net)
5.02 0.15 19.27 ^ _121_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.27 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
0.12 65.42 library setup time
65.42 data required time
-----------------------------------------------------------------------------
65.42 data required time
-19.27 data arrival time
-----------------------------------------------------------------------------
46.15 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.01 3.67 4.28 ^ _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
5.02 0.14 4.42 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.43 0.89 5.32 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[2] (net)
0.43 0.00 5.32 ^ io_out[2] (out)
5.32 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.32 data arrival time
-----------------------------------------------------------------------------
46.43 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _111_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.22 2.64 18.78 ^ _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
4.22 0.04 18.82 ^ _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.82 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.02 65.32 library setup time
65.32 data required time
-----------------------------------------------------------------------------
65.32 data required time
-18.82 data arrival time
-----------------------------------------------------------------------------
46.50 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.69 0.77 15.77 ^ _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.69 0.00 15.77 ^ _108_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.37 0.26 16.04 v _108_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _054_ (net)
0.37 0.00 16.04 v _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.46 2.77 18.80 ^ _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.15 _018_ (net)
4.46 0.04 18.84 ^ _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.84 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.05 65.35 library setup time
65.35 data required time
-----------------------------------------------------------------------------
65.35 data required time
-18.84 data arrival time
-----------------------------------------------------------------------------
46.50 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.88 3.60 4.20 ^ _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
4.90 0.14 4.34 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.43 0.89 5.22 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[18] (net)
0.43 0.00 5.22 ^ io_out[18] (out)
5.22 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.22 data arrival time
-----------------------------------------------------------------------------
46.53 slack (MET)
Startpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.68 3.47 4.07 ^ _123_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.29 net19 (net)
4.69 0.13 4.20 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.42 0.87 5.08 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[7] (net)
0.42 0.00 5.08 ^ io_out[7] (out)
5.08 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.08 data arrival time
-----------------------------------------------------------------------------
46.67 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.64 3.46 4.06 ^ _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
4.65 0.13 4.18 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.42 0.87 5.05 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[14] (net)
0.42 0.00 5.05 ^ io_out[14] (out)
5.05 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.05 data arrival time
-----------------------------------------------------------------------------
46.70 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.61 3.43 4.04 ^ _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
4.62 0.13 4.17 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.42 0.87 5.04 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[8] (net)
0.42 0.00 5.04 ^ io_out[8] (out)
5.04 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.04 data arrival time
-----------------------------------------------------------------------------
46.71 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.43 3.34 3.94 ^ _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
4.44 0.11 4.06 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.42 0.86 4.92 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[12] (net)
0.42 0.00 4.92 ^ io_out[12] (out)
4.92 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.92 data arrival time
-----------------------------------------------------------------------------
46.83 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.39 3.31 3.92 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.27 net3 (net)
4.40 0.11 4.03 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.42 0.86 4.89 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[10] (net)
0.42 0.00 4.89 ^ io_out[10] (out)
4.89 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.89 data arrival time
-----------------------------------------------------------------------------
46.86 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.25 2.63 3.24 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
3.26 0.08 3.32 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.27 0.90 4.22 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net25 (net)
1.27 0.01 4.22 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.35 0.62 4.84 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[1] (net)
0.35 0.00 4.85 ^ io_out[1] (out)
4.85 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.85 data arrival time
-----------------------------------------------------------------------------
46.90 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _094_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.38 0.27 16.00 v _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _045_ (net)
0.38 0.00 16.00 v _095_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.92 1.85 17.85 ^ _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.19 _013_ (net)
2.92 0.08 17.92 ^ _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.92 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
-0.12 65.17 library setup time
65.17 data required time
-----------------------------------------------------------------------------
65.17 data required time
-17.92 data arrival time
-----------------------------------------------------------------------------
47.25 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.77 2.94 3.54 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.24 net10 (net)
3.78 0.10 3.64 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.41 0.82 4.46 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[17] (net)
0.41 0.00 4.46 ^ io_out[17] (out)
4.46 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.46 data arrival time
-----------------------------------------------------------------------------
47.29 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.09 0.04 13.04 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.09 0.00 13.04 v input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.59 1.73 14.78 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.64 0.20 14.97 v _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.67 0.91 15.89 v _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.67 0.00 15.89 v _074_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.47 0.42 16.31 ^ _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _033_ (net)
0.47 0.00 16.31 ^ _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.38 0.91 17.22 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.17 _005_ (net)
1.39 0.06 17.28 v _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.28 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.24 65.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 65.55 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.30 clock uncertainty
0.00 65.30 clock reconvergence pessimism
-0.67 64.63 library setup time
64.63 data required time
-----------------------------------------------------------------------------
64.63 data required time
-17.28 data arrival time
-----------------------------------------------------------------------------
47.35 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.67 2.88 3.48 ^ _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
3.68 0.09 3.57 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.81 4.39 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[13] (net)
0.40 0.00 4.39 ^ io_out[13] (out)
4.39 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.39 data arrival time
-----------------------------------------------------------------------------
47.36 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.62 2.85 3.46 ^ _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net12 (net)
3.62 0.09 3.55 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.81 4.37 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[19] (net)
0.40 0.00 4.37 ^ io_out[19] (out)
4.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.37 data arrival time
-----------------------------------------------------------------------------
47.38 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.09 0.04 13.04 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.09 0.00 13.04 v input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.59 1.73 14.78 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.64 0.20 14.97 v _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.67 0.91 15.89 v _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.67 0.00 15.89 v _062_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.45 0.44 16.33 ^ _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _025_ (net)
0.45 0.00 16.33 ^ _063_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.29 0.88 17.20 v _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _001_ (net)
1.30 0.05 17.26 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.26 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
-0.64 64.65 library setup time
64.65 data required time
-----------------------------------------------------------------------------
64.65 data required time
-17.26 data arrival time
-----------------------------------------------------------------------------
47.39 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _104_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.36 0.25 15.98 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _051_ (net)
0.36 0.00 15.98 v _105_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2.55 1.63 17.61 ^ _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _017_ (net)
2.55 0.06 17.67 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.67 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
-0.16 65.14 library setup time
65.14 data required time
-----------------------------------------------------------------------------
65.14 data required time
-17.67 data arrival time
-----------------------------------------------------------------------------
47.47 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.46 2.75 3.36 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.22 net9 (net)
3.47 0.09 3.45 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.80 4.25 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[16] (net)
0.40 0.00 4.25 ^ io_out[16] (out)
4.25 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.25 data arrival time
-----------------------------------------------------------------------------
47.50 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.12 0.26 0.61 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.12 0.00 0.61 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.35 2.70 3.31 ^ _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
3.36 0.08 3.39 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.40 0.79 4.18 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[6] (net)
0.40 0.00 4.18 ^ io_out[6] (out)
4.18 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.18 data arrival time
-----------------------------------------------------------------------------
47.57 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.01 2.49 3.09 ^ _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
3.01 0.07 3.16 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.78 3.94 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[15] (net)
0.39 0.00 3.94 ^ io_out[15] (out)
3.94 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.94 data arrival time
-----------------------------------------------------------------------------
47.81 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.87 2.41 3.01 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
2.88 0.07 3.07 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.77 3.84 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[9] (net)
0.39 0.00 3.84 ^ io_out[9] (out)
3.84 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.84 data arrival time
-----------------------------------------------------------------------------
47.91 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.85 2.40 3.00 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
2.86 0.06 3.06 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.76 3.83 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[11] (net)
0.39 0.00 3.83 ^ io_out[11] (out)
3.83 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.83 data arrival time
-----------------------------------------------------------------------------
47.92 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.15 0.08 0.08 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.27 0.35 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.35 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.25 0.60 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 0.60 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.84 2.40 3.00 ^ _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net15 (net)
2.84 0.05 3.05 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.39 0.76 3.81 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[3] (net)
0.39 0.00 3.81 ^ io_out[3] (out)
3.81 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.81 data arrival time
-----------------------------------------------------------------------------
47.94 slack (MET)
======================= Fastest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.26 0.32 15.42 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.26 0.00 15.42 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.32 3.81 19.22 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
6.33 0.15 19.37 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.48 65.58 library setup time
65.58 data required time
-----------------------------------------------------------------------------
65.58 data required time
-19.37 data arrival time
-----------------------------------------------------------------------------
46.21 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.22 0.29 15.39 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.22 0.00 15.39 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.82 2.92 18.31 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.26 _004_ (net)
4.83 0.11 18.42 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.42 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.30 65.40 library setup time
65.40 data required time
-----------------------------------------------------------------------------
65.40 data required time
-18.42 data arrival time
-----------------------------------------------------------------------------
46.99 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.36 0.36 15.20 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.36 0.00 15.20 ^ _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.20 0.10 15.30 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _042_ (net)
0.20 0.00 15.30 v _089_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.84 2.93 18.23 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.27 _010_ (net)
4.85 0.11 18.34 ^ _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.34 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.31 65.42 library setup time
65.42 data required time
-----------------------------------------------------------------------------
65.42 data required time
-18.34 data arrival time
-----------------------------------------------------------------------------
47.08 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.26 0.32 15.42 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.26 0.00 15.42 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.56 2.77 18.19 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _011_ (net)
4.57 0.10 18.29 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.29 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.27 65.37 library setup time
65.37 data required time
-----------------------------------------------------------------------------
65.37 data required time
-18.29 data arrival time
-----------------------------------------------------------------------------
47.08 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.22 0.29 15.39 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.22 0.00 15.39 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.49 2.72 18.11 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _012_ (net)
4.50 0.10 18.21 ^ _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.21 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.27 65.37 library setup time
65.37 data required time
-----------------------------------------------------------------------------
65.37 data required time
-18.21 data arrival time
-----------------------------------------------------------------------------
47.16 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.26 0.32 15.42 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.26 0.00 15.42 v _071_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.35 2.65 18.07 ^ _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.24 _003_ (net)
4.36 0.09 18.16 ^ _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.16 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.25 65.36 library setup time
65.36 data required time
-----------------------------------------------------------------------------
65.36 data required time
-18.16 data arrival time
-----------------------------------------------------------------------------
47.19 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.36 0.36 15.20 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.36 0.00 15.20 ^ _098_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.18 0.09 15.29 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _048_ (net)
0.18 0.00 15.29 v _099_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.48 2.71 18.00 ^ _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.25 _014_ (net)
4.49 0.10 18.10 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
18.10 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.27 65.37 library setup time
65.37 data required time
-----------------------------------------------------------------------------
65.37 data required time
-18.10 data arrival time
-----------------------------------------------------------------------------
47.27 slack (MET)
Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.21 2.91 3.30 ^ _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.40 net2 (net)
4.23 0.19 3.49 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.30 0.69 4.17 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[0] (net)
0.30 0.00 4.18 ^ io_out[0] (out)
4.18 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.18 data arrival time
-----------------------------------------------------------------------------
47.57 slack (MET)
Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.81 2.68 3.07 ^ _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.36 net17 (net)
3.83 0.16 3.23 ^ fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.80 0.45 3.68 ^ fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net24 (net)
0.80 0.00 3.68 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.23 0.41 4.09 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[5] (net)
0.23 0.00 4.10 ^ io_out[5] (out)
4.10 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.10 data arrival time
-----------------------------------------------------------------------------
47.65 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.26 0.32 15.42 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.26 0.00 15.42 v _103_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.36 2.06 17.47 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _016_ (net)
3.37 0.07 17.55 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.55 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.13 65.24 library setup time
65.24 data required time
-----------------------------------------------------------------------------
65.24 data required time
-17.55 data arrival time
-----------------------------------------------------------------------------
47.69 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.22 0.29 15.39 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.22 0.00 15.39 v _083_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.41 2.08 17.48 ^ _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _008_ (net)
3.41 0.07 17.54 ^ _120_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.54 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.13 65.24 library setup time
65.24 data required time
-----------------------------------------------------------------------------
65.24 data required time
-17.54 data arrival time
-----------------------------------------------------------------------------
47.69 slack (MET)
Startpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.03 2.80 3.19 ^ _120_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.38 net16 (net)
4.06 0.18 3.37 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.30 0.67 4.04 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[4] (net)
0.30 0.00 4.04 ^ io_out[4] (out)
4.04 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.04 data arrival time
-----------------------------------------------------------------------------
47.71 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.22 0.29 15.39 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _023_ (net)
0.22 0.00 15.39 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.30 2.02 17.41 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.18 _000_ (net)
3.30 0.07 17.48 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.48 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.13 65.23 library setup time
65.23 data required time
-----------------------------------------------------------------------------
65.23 data required time
-17.48 data arrival time
-----------------------------------------------------------------------------
47.75 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.65 2.24 17.34 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.20 _015_ (net)
3.65 0.07 17.42 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.42 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.16 65.27 library setup time
65.27 data required time
-----------------------------------------------------------------------------
65.27 data required time
-17.42 data arrival time
-----------------------------------------------------------------------------
47.85 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.36 0.36 15.20 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.36 0.00 15.20 ^ _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.22 0.10 15.30 v _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _029_ (net)
0.22 0.00 15.30 v _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.21 1.97 17.27 ^ _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.17 _002_ (net)
3.21 0.06 17.33 ^ _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.33 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.11 65.21 library setup time
65.21 data required time
-----------------------------------------------------------------------------
65.21 data required time
-17.33 data arrival time
-----------------------------------------------------------------------------
47.88 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _065_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.36 0.36 15.20 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _027_ (net)
0.36 0.00 15.20 ^ _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.21 0.10 15.30 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _036_ (net)
0.21 0.00 15.30 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.95 1.82 17.12 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _006_ (net)
2.96 0.06 17.18 ^ _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
17.18 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.08 65.19 library setup time
65.19 data required time
-----------------------------------------------------------------------------
65.19 data required time
-17.18 data arrival time
-----------------------------------------------------------------------------
48.02 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.06 0.03 13.03 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.06 0.00 13.03 v input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.69 1.08 14.11 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.76 0.20 14.31 v _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.43 0.58 14.89 v _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.43 0.00 14.89 v _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.32 0.29 15.18 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _039_ (net)
0.32 0.00 15.18 ^ _085_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
1.63 0.97 16.15 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.33 _009_ (net)
1.66 0.15 16.29 v _121_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
16.29 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
-0.68 64.43 library setup time
64.43 data required time
-----------------------------------------------------------------------------
64.43 data required time
-16.29 data arrival time
-----------------------------------------------------------------------------
48.14 slack (MET)
Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.33 2.40 2.79 ^ _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net14 (net)
3.35 0.14 2.93 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.62 3.56 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[2] (net)
0.28 0.00 3.56 ^ io_out[2] (out)
3.56 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.56 data arrival time
-----------------------------------------------------------------------------
48.19 slack (MET)
Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.25 2.35 2.74 ^ _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.31 net11 (net)
3.26 0.14 2.88 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.62 3.49 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[18] (net)
0.28 0.00 3.50 ^ io_out[18] (out)
3.50 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.50 data arrival time
-----------------------------------------------------------------------------
48.25 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _111_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.62 1.65 16.75 ^ _111_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
2.62 0.04 16.79 ^ _131_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
16.79 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.04 65.14 library setup time
65.14 data required time
-----------------------------------------------------------------------------
65.14 data required time
-16.79 data arrival time
-----------------------------------------------------------------------------
48.36 slack (MET)
Startpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.11 2.26 2.65 ^ _123_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.29 net19 (net)
3.13 0.13 2.78 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.61 3.39 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[7] (net)
0.28 0.00 3.39 ^ io_out[7] (out)
3.39 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.39 data arrival time
-----------------------------------------------------------------------------
48.36 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.45 0.51 14.86 ^ _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.45 0.00 14.86 ^ _108_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.25 0.17 15.03 v _108_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _054_ (net)
0.25 0.00 15.03 v _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.77 1.73 16.76 ^ _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.15 _018_ (net)
2.77 0.04 16.80 ^ _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
16.80 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.06 65.16 library setup time
65.16 data required time
-----------------------------------------------------------------------------
65.16 data required time
-16.80 data arrival time
-----------------------------------------------------------------------------
48.36 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.08 2.26 2.65 ^ _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net7 (net)
3.10 0.12 2.77 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.61 3.38 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[14] (net)
0.28 0.00 3.38 ^ io_out[14] (out)
3.38 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.38 data arrival time
-----------------------------------------------------------------------------
48.37 slack (MET)
Startpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.06 2.24 2.63 ^ _124_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.29 net20 (net)
3.08 0.13 2.76 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.61 3.36 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[8] (net)
0.28 0.00 3.37 ^ io_out[8] (out)
3.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.37 data arrival time
-----------------------------------------------------------------------------
48.38 slack (MET)
Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.94 2.18 2.57 ^ _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.28 net5 (net)
2.96 0.11 2.69 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.60 3.28 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[12] (net)
0.28 0.00 3.29 ^ io_out[12] (out)
3.29 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.29 data arrival time
-----------------------------------------------------------------------------
48.46 slack (MET)
Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.92 2.16 2.56 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.27 net3 (net)
2.93 0.11 2.67 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.28 0.59 3.26 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[10] (net)
0.28 0.00 3.26 ^ io_out[10] (out)
3.26 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.26 data arrival time
-----------------------------------------------------------------------------
48.49 slack (MET)
Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.16 1.71 2.10 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net13 (net)
2.16 0.08 2.18 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.83 0.58 2.76 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.07 net25 (net)
0.83 0.01 2.77 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.23 0.41 3.18 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[1] (net)
0.23 0.00 3.18 ^ io_out[1] (out)
3.18 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.18 data arrival time
-----------------------------------------------------------------------------
48.57 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.51 1.91 2.30 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.24 net10 (net)
2.52 0.10 2.40 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.27 0.57 2.97 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[17] (net)
0.27 0.00 2.97 ^ io_out[17] (out)
2.97 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.97 data arrival time
-----------------------------------------------------------------------------
48.78 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.06 0.03 13.03 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.06 0.00 13.03 v input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.69 1.08 14.11 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.76 0.20 14.31 v _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.38 0.55 14.86 v _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.38 0.00 14.86 v _094_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.31 0.28 15.14 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _045_ (net)
0.31 0.00 15.14 ^ _095_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
0.94 0.62 15.76 v _095_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.19 _013_ (net)
0.96 0.08 15.83 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
15.83 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
-0.45 64.65 library setup time
64.65 data required time
-----------------------------------------------------------------------------
64.65 data required time
-15.83 data arrival time
-----------------------------------------------------------------------------
48.82 slack (MET)
Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.44 1.88 2.27 ^ _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net6 (net)
2.45 0.09 2.36 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.27 0.56 2.92 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[13] (net)
0.27 0.00 2.92 ^ io_out[13] (out)
2.92 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.92 data arrival time
-----------------------------------------------------------------------------
48.83 slack (MET)
Startpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.40 1.86 2.25 ^ _115_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.22 net12 (net)
2.41 0.09 2.34 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.27 0.56 2.90 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[19] (net)
0.27 0.00 2.90 ^ io_out[19] (out)
2.90 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.90 data arrival time
-----------------------------------------------------------------------------
48.85 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.06 0.03 13.03 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.06 0.00 13.03 v input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.69 1.08 14.11 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.76 0.20 14.31 v _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.43 0.58 14.89 v _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.43 0.00 14.89 v _074_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.30 0.27 15.17 ^ _074_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _033_ (net)
0.30 0.00 15.17 ^ _075_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
0.88 0.58 15.75 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.17 _005_ (net)
0.89 0.06 15.81 v _117_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
15.81 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
-0.42 64.68 library setup time
64.68 data required time
-----------------------------------------------------------------------------
64.68 data required time
-15.81 data arrival time
-----------------------------------------------------------------------------
48.88 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.06 0.03 13.03 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.06 0.00 13.03 v input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.69 1.08 14.11 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.76 0.20 14.31 v _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.43 0.58 14.89 v _061_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.04 _024_ (net)
0.43 0.00 14.89 v _062_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.30 0.28 15.18 ^ _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _025_ (net)
0.30 0.00 15.18 ^ _063_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
0.82 0.57 15.74 v _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _001_ (net)
0.83 0.05 15.80 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
15.80 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
-0.40 64.70 library setup time
64.70 data required time
-----------------------------------------------------------------------------
64.70 data required time
-15.80 data arrival time
-----------------------------------------------------------------------------
48.90 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.29 1.79 2.18 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net9 (net)
2.30 0.09 2.27 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.55 2.82 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[16] (net)
0.26 0.00 2.82 ^ io_out[16] (out)
2.82 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.82 data arrival time
-----------------------------------------------------------------------------
48.93 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.06 0.03 13.03 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.06 0.00 13.03 v input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.69 1.08 14.11 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.76 0.20 14.31 v _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.38 0.55 14.86 v _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.38 0.00 14.86 v _104_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.28 0.26 15.12 ^ _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _051_ (net)
0.28 0.00 15.12 ^ _105_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
0.82 0.55 15.68 v _105_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_2)
2 0.16 _017_ (net)
0.83 0.06 15.74 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
15.74 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
-0.40 64.70 library setup time
64.70 data required time
-----------------------------------------------------------------------------
64.70 data required time
-15.74 data arrival time
-----------------------------------------------------------------------------
48.96 slack (MET)
Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.05 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.22 1.75 2.15 ^ _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.21 net18 (net)
2.23 0.08 2.23 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.54 2.77 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[6] (net)
0.26 0.00 2.78 ^ io_out[6] (out)
2.78 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.78 data arrival time
-----------------------------------------------------------------------------
48.97 slack (MET)
Startpoint: _131_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _131_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.00 1.62 2.01 ^ _131_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.19 net8 (net)
2.00 0.07 2.08 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.53 2.61 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[15] (net)
0.26 0.00 2.61 ^ io_out[15] (out)
2.61 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.61 data arrival time
-----------------------------------------------------------------------------
49.14 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.90 1.56 1.95 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net21 (net)
1.91 0.07 2.02 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.52 2.54 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[9] (net)
0.26 0.00 2.54 ^ io_out[9] (out)
2.54 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.54 data arrival time
-----------------------------------------------------------------------------
49.21 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.89 1.56 1.95 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.18 net4 (net)
1.90 0.06 2.01 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.26 0.52 2.53 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[11] (net)
0.26 0.00 2.53 ^ io_out[11] (out)
2.53 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.53 data arrival time
-----------------------------------------------------------------------------
49.22 slack (MET)
Startpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 0.39 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 0.39 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.88 1.56 1.95 ^ _119_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
1.88 0.05 2.00 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.25 0.52 2.52 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[3] (net)
0.25 0.00 2.52 ^ io_out[3] (out)
2.52 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.52 data arrival time
-----------------------------------------------------------------------------
49.23 slack (MET)
max_report_end
check_report
===========================================================================
report_checks -unconstrained
============================================================================
======================= Slowest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.28 0.12 13.12 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.28 0.00 13.12 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4.57 3.05 16.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
4.60 0.20 16.37 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1.07 1.27 17.64 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
1.07 0.00 17.64 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.82 0.74 18.38 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.82 0.00 18.38 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.71 0.88 19.26 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.71 0.00 19.26 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
18.30 11.18 30.43 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
18.30 0.15 30.58 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
30.58 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.27 0.12 65.12 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.27 0.00 65.12 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.20 0.44 65.55 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.20 0.00 65.55 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.41 65.97 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.97 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.72 clock uncertainty
0.00 65.72 clock reconvergence pessimism
0.87 66.59 library setup time
66.59 data required time
-----------------------------------------------------------------------------
66.59 data required time
-30.58 data arrival time
-----------------------------------------------------------------------------
36.01 slack (MET)
======================= Typical Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.16 0.07 13.07 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.16 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
2.68 1.73 14.80 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
2.72 0.20 15.00 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.62 0.72 15.72 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.62 0.00 15.72 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.47 0.42 16.14 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.47 0.00 16.14 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.49 16.63 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.40 0.00 16.63 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
10.13 6.14 22.77 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
10.13 0.15 22.92 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
22.92 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.15 0.07 65.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.15 0.00 65.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 65.31 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 65.31 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.23 65.54 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.11 0.00 65.54 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.29 clock uncertainty
0.00 65.29 clock reconvergence pessimism
0.70 65.99 library setup time
65.99 data required time
-----------------------------------------------------------------------------
65.99 data required time
-22.92 data arrival time
-----------------------------------------------------------------------------
43.07 slack (MET)
======================= Fastest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.10 0.05 13.05 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.10 0.00 13.05 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
1.77 1.11 14.16 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2)
4 0.34 net1 (net)
1.83 0.20 14.35 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.40 0.48 14.83 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
8 0.03 _021_ (net)
0.40 0.00 14.83 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.30 0.27 15.10 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _022_ (net)
0.30 0.00 15.10 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.26 0.32 15.42 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.02 _030_ (net)
0.26 0.00 15.42 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.32 3.81 19.22 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.35 _007_ (net)
6.33 0.15 19.37 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.16 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.35 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
11 0.04 clknet_1_0__leaf_wb_clk_i (net)
0.07 0.00 65.35 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.10 clock uncertainty
0.00 65.10 clock reconvergence pessimism
0.48 65.58 library setup time
65.58 data required time
-----------------------------------------------------------------------------
65.58 data required time
-19.37 data arrival time
-----------------------------------------------------------------------------
46.21 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= Slowest Corner ===================================
No paths found.
======================= Typical Corner ===================================
No paths found.
======================= Fastest Corner ===================================
No paths found.
check_report_end
check_slew
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= Slowest Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------
ANTENNA__119__D/I 7.00 18.30 -11.30 (VIOLATED)
_119_/D 7.00 18.30 -11.30 (VIOLATED)
_081_/ZN 7.00 18.30 -11.30 (VIOLATED)
ANTENNA__122__D/I 7.00 14.00 -7.00 (VIOLATED)
_122_/D 7.00 14.00 -7.00 (VIOLATED)
_089_/ZN 7.00 14.00 -7.00 (VIOLATED)
ANTENNA__116__D/I 7.00 13.94 -6.94 (VIOLATED)
_116_/D 7.00 13.94 -6.94 (VIOLATED)
_073_/ZN 7.00 13.94 -6.94 (VIOLATED)
ANTENNA__123__D/I 7.00 13.22 -6.22 (VIOLATED)
_123_/D 7.00 13.22 -6.22 (VIOLATED)
_091_/ZN 7.00 13.22 -6.22 (VIOLATED)
ANTENNA__124__D/I 7.00 12.99 -5.99 (VIOLATED)
_124_/D 7.00 12.99 -5.99 (VIOLATED)
_093_/ZN 7.00 12.98 -5.98 (VIOLATED)
ANTENNA__126__D/I 7.00 12.96 -5.96 (VIOLATED)
_126_/D 7.00 12.96 -5.96 (VIOLATED)
_099_/ZN 7.00 12.95 -5.95 (VIOLATED)
ANTENNA__115__D/I 7.00 12.62 -5.62 (VIOLATED)
_115_/D 7.00 12.62 -5.62 (VIOLATED)
_071_/ZN 7.00 12.62 -5.62 (VIOLATED)
ANTENNA_output2_I/I 7.00 10.80 -3.80 (VIOLATED)
output2/I 7.00 10.80 -3.80 (VIOLATED)
ANTENNA__072__I/I 7.00 10.80 -3.80 (VIOLATED)
_072_/I 7.00 10.80 -3.80 (VIOLATED)
ANTENNA__077__A1/I 7.00 10.80 -3.80 (VIOLATED)
_077_/A1 7.00 10.80 -3.80 (VIOLATED)
_116_/Q 7.00 10.79 -3.79 (VIOLATED)
ANTENNA__127__D/I 7.00 10.58 -3.58 (VIOLATED)
_127_/D 7.00 10.58 -3.58 (VIOLATED)
_101_/ZN 7.00 10.58 -3.58 (VIOLATED)
output16/I 7.00 10.35 -3.35 (VIOLATED)
ANTENNA_output16_I/I 7.00 10.35 -3.35 (VIOLATED)
_082_/I 7.00 10.34 -3.34 (VIOLATED)
ANTENNA__082__I/I 7.00 10.34 -3.34 (VIOLATED)
_087_/A1 7.00 10.34 -3.34 (VIOLATED)
ANTENNA__087__A1/I 7.00 10.34 -3.34 (VIOLATED)
_120_/Q 7.00 10.34 -3.34 (VIOLATED)
ANTENNA__120__D/I 7.00 9.87 -2.87 (VIOLATED)
_120_/D 7.00 9.87 -2.87 (VIOLATED)
_083_/ZN 7.00 9.86 -2.86 (VIOLATED)
_087_/A2 7.00 9.77 -2.77 (VIOLATED)
ANTENNA__087__A2/I 7.00 9.77 -2.77 (VIOLATED)
ANTENNA_fanout24_I/I 7.00 9.77 -2.77 (VIOLATED)
fanout24/I 7.00 9.77 -2.77 (VIOLATED)
_121_/Q 7.00 9.77 -2.77 (VIOLATED)
ANTENNA__128__D/I 7.00 9.75 -2.75 (VIOLATED)
_128_/D 7.00 9.75 -2.75 (VIOLATED)
_103_/ZN 7.00 9.75 -2.75 (VIOLATED)
ANTENNA__112__D/I 7.00 9.57 -2.57 (VIOLATED)
_112_/D 7.00 9.57 -2.57 (VIOLATED)
_060_/ZN 7.00 9.57 -2.57 (VIOLATED)
ANTENNA__114__D/I 7.00 9.31 -2.31 (VIOLATED)
_114_/D 7.00 9.31 -2.31 (VIOLATED)
_068_/ZN 7.00 9.31 -2.31 (VIOLATED)
ANTENNA__121__D/I 7.00 9.08 -2.08 (VIOLATED)
_121_/D 7.00 9.08 -2.08 (VIOLATED)
_085_/ZN 7.00 9.07 -2.07 (VIOLATED)
ANTENNA__118__D/I 7.00 8.57 -1.57 (VIOLATED)
_118_/D 7.00 8.57 -1.57 (VIOLATED)
_079_/ZN 7.00 8.57 -1.57 (VIOLATED)
output14/I 7.00 8.56 -1.56 (VIOLATED)
ANTENNA_output14_I/I 7.00 8.56 -1.56 (VIOLATED)
_076_/B 7.00 8.56 -1.56 (VIOLATED)
_077_/A3 7.00 8.56 -1.56 (VIOLATED)
ANTENNA__077__A3/I 7.00 8.56 -1.56 (VIOLATED)
ANTENNA__076__B/I 7.00 8.56 -1.56 (VIOLATED)
_118_/Q 7.00 8.56 -1.56 (VIOLATED)
output11/I 7.00 8.34 -1.34 (VIOLATED)
ANTENNA_output11_I/I 7.00 8.34 -1.34 (VIOLATED)
_064_/B 7.00 8.34 -1.34 (VIOLATED)
ANTENNA__064__B/I 7.00 8.34 -1.34 (VIOLATED)
ANTENNA__066__A3/I 7.00 8.34 -1.34 (VIOLATED)
_066_/A3 7.00 8.34 -1.34 (VIOLATED)
_114_/Q 7.00 8.34 -1.34 (VIOLATED)
ANTENNA__130__D/I 7.00 8.03 -1.03 (VIOLATED)
_130_/D 7.00 8.03 -1.03 (VIOLATED)
_109_/ZN 7.00 8.03 -1.03 (VIOLATED)
output19/I 7.00 7.99 -0.99 (VIOLATED)
ANTENNA_output19_I/I 7.00 7.99 -0.99 (VIOLATED)
_090_/A1 7.00 7.99 -0.99 (VIOLATED)
ANTENNA__090__A1/I 7.00 7.99 -0.99 (VIOLATED)
_123_/Q 7.00 7.99 -0.99 (VIOLATED)
ANTENNA_output7_I/I 7.00 7.92 -0.92 (VIOLATED)
output7/I 7.00 7.92 -0.92 (VIOLATED)
_106_/B 7.00 7.92 -0.92 (VIOLATED)
ANTENNA__106__B/I 7.00 7.92 -0.92 (VIOLATED)
_107_/A3 7.00 7.92 -0.92 (VIOLATED)
ANTENNA__107__A3/I 7.00 7.92 -0.92 (VIOLATED)
_130_/Q 7.00 7.92 -0.92 (VIOLATED)
output20/I 7.00 7.88 -0.88 (VIOLATED)
ANTENNA_output20_I/I 7.00 7.88 -0.88 (VIOLATED)
ANTENNA__092__I/I 7.00 7.88 -0.88 (VIOLATED)
_092_/I 7.00 7.88 -0.88 (VIOLATED)
ANTENNA__097__A1/I 7.00 7.88 -0.88 (VIOLATED)
_097_/A1 7.00 7.88 -0.88 (VIOLATED)
_124_/Q 7.00 7.87 -0.87 (VIOLATED)
_131_/D 7.00 7.60 -0.60 (VIOLATED)
ANTENNA__131__D/I 7.00 7.60 -0.60 (VIOLATED)
_111_/ZN 7.00 7.59 -0.59 (VIOLATED)
output5/I 7.00 7.57 -0.57 (VIOLATED)
ANTENNA_output5_I/I 7.00 7.57 -0.57 (VIOLATED)
_107_/A1 7.00 7.57 -0.57 (VIOLATED)
ANTENNA__107__A1/I 7.00 7.57 -0.57 (VIOLATED)
ANTENNA__102__I/I 7.00 7.57 -0.57 (VIOLATED)
_102_/I 7.00 7.57 -0.57 (VIOLATED)
_128_/Q 7.00 7.56 -0.56 (VIOLATED)
output3/I 7.00 7.50 -0.50 (VIOLATED)
ANTENNA_output3_I/I 7.00 7.50 -0.50 (VIOLATED)
ANTENNA__096__B/I 7.00 7.50 -0.50 (VIOLATED)
_096_/B 7.00 7.50 -0.50 (VIOLATED)
_097_/A3 7.00 7.50 -0.50 (VIOLATED)
ANTENNA__097__A3/I 7.00 7.50 -0.50 (VIOLATED)
_126_/Q 7.00 7.50 -0.50 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
clkbuf_1_1__f_wb_clk_i/Z 4 18 -14 (VIOLATED)
clkbuf_1_0__f_wb_clk_i/Z 4 11 -7 (VIOLATED)
_056_/Z 4 8 -4 (VIOLATED)
_057_/Z 4 8 -4 (VIOLATED)
_061_/Z 4 8 -4 (VIOLATED)
_065_/Z 4 8 -4 (VIOLATED)
_072_/Z 4 8 -4 (VIOLATED)
_082_/Z 4 8 -4 (VIOLATED)
_092_/Z 4 8 -4 (VIOLATED)
_102_/Z 4 8 -4 (VIOLATED)
fanout22/Z 4 8 -4 (VIOLATED)
fanout23/Z 4 8 -4 (VIOLATED)
fanout24/Z 4 8 -4 (VIOLATED)
fanout25/Z 4 8 -4 (VIOLATED)
fanout26/Z 4 8 -4 (VIOLATED)
_112_/Q 4 6 -2 (VIOLATED)
_114_/Q 4 6 -2 (VIOLATED)
_116_/Q 4 6 -2 (VIOLATED)
_118_/Q 4 6 -2 (VIOLATED)
_120_/Q 4 6 -2 (VIOLATED)
_122_/Q 4 6 -2 (VIOLATED)
_124_/Q 4 6 -2 (VIOLATED)
_126_/Q 4 6 -2 (VIOLATED)
_128_/Q 4 6 -2 (VIOLATED)
_130_/Q 4 6 -2 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
_081_/ZN 0.12 0.35 -0.23 (VIOLATED)
_116_/Q 0.25 0.40 -0.15 (VIOLATED)
_089_/ZN 0.12 0.27 -0.14 (VIOLATED)
_073_/ZN 0.12 0.26 -0.14 (VIOLATED)
_120_/Q 0.25 0.38 -0.13 (VIOLATED)
_091_/ZN 0.12 0.25 -0.13 (VIOLATED)
_093_/ZN 0.12 0.25 -0.12 (VIOLATED)
_099_/ZN 0.12 0.25 -0.12 (VIOLATED)
_071_/ZN 0.12 0.24 -0.12 (VIOLATED)
_121_/Q 0.25 0.36 -0.11 (VIOLATED)
_085_/ZN 0.24 0.33 -0.09 (VIOLATED)
_101_/ZN 0.12 0.20 -0.08 (VIOLATED)
_118_/Q 0.25 0.31 -0.07 (VIOLATED)
_083_/ZN 0.12 0.19 -0.06 (VIOLATED)
_103_/ZN 0.12 0.18 -0.06 (VIOLATED)
_114_/Q 0.25 0.31 -0.06 (VIOLATED)
_060_/ZN 0.12 0.18 -0.06 (VIOLATED)
_068_/ZN 0.12 0.17 -0.05 (VIOLATED)
_123_/Q 0.25 0.29 -0.05 (VIOLATED)
_130_/Q 0.25 0.29 -0.04 (VIOLATED)
_124_/Q 0.25 0.29 -0.04 (VIOLATED)
_079_/ZN 0.12 0.16 -0.04 (VIOLATED)
_128_/Q 0.25 0.28 -0.03 (VIOLATED)
_109_/ZN 0.12 0.15 -0.03 (VIOLATED)
_126_/Q 0.25 0.28 -0.03 (VIOLATED)
_111_/ZN 0.12 0.14 -0.02 (VIOLATED)
======================= Typical Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------
ANTENNA__119__D/I 4.00 10.13 -6.13 (VIOLATED)
_119_/D 4.00 10.13 -6.13 (VIOLATED)
_081_/ZN 4.00 10.13 -6.13 (VIOLATED)
ANTENNA__122__D/I 4.00 7.77 -3.77 (VIOLATED)
_122_/D 4.00 7.77 -3.77 (VIOLATED)
_089_/ZN 4.00 7.76 -3.76 (VIOLATED)
ANTENNA__116__D/I 4.00 7.73 -3.73 (VIOLATED)
_116_/D 4.00 7.73 -3.73 (VIOLATED)
_073_/ZN 4.00 7.73 -3.73 (VIOLATED)
ANTENNA__123__D/I 4.00 7.32 -3.32 (VIOLATED)
_123_/D 4.00 7.32 -3.32 (VIOLATED)
_091_/ZN 4.00 7.31 -3.31 (VIOLATED)
ANTENNA__126__D/I 4.00 7.20 -3.20 (VIOLATED)
_126_/D 4.00 7.20 -3.20 (VIOLATED)
_124_/D 4.00 7.20 -3.20 (VIOLATED)
ANTENNA__124__D/I 4.00 7.20 -3.20 (VIOLATED)
_099_/ZN 4.00 7.20 -3.20 (VIOLATED)
_093_/ZN 4.00 7.20 -3.20 (VIOLATED)
ANTENNA__115__D/I 4.00 6.98 -2.98 (VIOLATED)
_115_/D 4.00 6.98 -2.98 (VIOLATED)
_071_/ZN 4.00 6.98 -2.98 (VIOLATED)
output2/I 4.00 6.34 -2.34 (VIOLATED)
ANTENNA_output2_I/I 4.00 6.34 -2.34 (VIOLATED)
ANTENNA__072__I/I 4.00 6.34 -2.34 (VIOLATED)
_072_/I 4.00 6.34 -2.34 (VIOLATED)
ANTENNA__077__A1/I 4.00 6.34 -2.34 (VIOLATED)
_077_/A1 4.00 6.34 -2.34 (VIOLATED)
_116_/Q 4.00 6.32 -2.32 (VIOLATED)
output16/I 4.00 6.07 -2.07 (VIOLATED)
ANTENNA_output16_I/I 4.00 6.07 -2.07 (VIOLATED)
_082_/I 4.00 6.07 -2.07 (VIOLATED)
ANTENNA__082__I/I 4.00 6.07 -2.07 (VIOLATED)
_087_/A1 4.00 6.07 -2.07 (VIOLATED)
ANTENNA__087__A1/I 4.00 6.07 -2.07 (VIOLATED)
_120_/Q 4.00 6.05 -2.05 (VIOLATED)
ANTENNA__127__D/I 4.00 5.85 -1.85 (VIOLATED)
_127_/D 4.00 5.85 -1.85 (VIOLATED)
_101_/ZN 4.00 5.84 -1.84 (VIOLATED)
_087_/A2 4.00 5.74 -1.74 (VIOLATED)
ANTENNA__087__A2/I 4.00 5.74 -1.74 (VIOLATED)
ANTENNA_fanout24_I/I 4.00 5.74 -1.74 (VIOLATED)
fanout24/I 4.00 5.74 -1.74 (VIOLATED)
_121_/Q 4.00 5.73 -1.73 (VIOLATED)
ANTENNA__120__D/I 4.00 5.46 -1.46 (VIOLATED)
_120_/D 4.00 5.46 -1.46 (VIOLATED)
_083_/ZN 4.00 5.46 -1.46 (VIOLATED)
ANTENNA__128__D/I 4.00 5.39 -1.39 (VIOLATED)
_128_/D 4.00 5.39 -1.39 (VIOLATED)
_103_/ZN 4.00 5.39 -1.39 (VIOLATED)
ANTENNA__112__D/I 4.00 5.29 -1.29 (VIOLATED)
_112_/D 4.00 5.29 -1.29 (VIOLATED)
_060_/ZN 4.00 5.29 -1.29 (VIOLATED)
_114_/D 4.00 5.16 -1.16 (VIOLATED)
ANTENNA__114__D/I 4.00 5.16 -1.16 (VIOLATED)
_068_/ZN 4.00 5.15 -1.15 (VIOLATED)
output14/I 4.00 5.02 -1.02 (VIOLATED)
ANTENNA_output14_I/I 4.00 5.02 -1.02 (VIOLATED)
_076_/B 4.00 5.02 -1.02 (VIOLATED)
_077_/A3 4.00 5.02 -1.02 (VIOLATED)
ANTENNA__077__A3/I 4.00 5.02 -1.02 (VIOLATED)
ANTENNA__076__B/I 4.00 5.02 -1.02 (VIOLATED)
ANTENNA__121__D/I 4.00 5.02 -1.02 (VIOLATED)
_121_/D 4.00 5.02 -1.02 (VIOLATED)
_118_/Q 4.00 5.01 -1.01 (VIOLATED)
_085_/ZN 4.00 5.01 -1.01 (VIOLATED)
output11/I 4.00 4.90 -0.90 (VIOLATED)
ANTENNA_output11_I/I 4.00 4.90 -0.90 (VIOLATED)
_064_/B 4.00 4.90 -0.90 (VIOLATED)
ANTENNA__064__B/I 4.00 4.90 -0.90 (VIOLATED)
ANTENNA__066__A3/I 4.00 4.90 -0.90 (VIOLATED)
_066_/A3 4.00 4.90 -0.90 (VIOLATED)
_114_/Q 4.00 4.88 -0.88 (VIOLATED)
ANTENNA__118__D/I 4.00 4.75 -0.75 (VIOLATED)
_118_/D 4.00 4.75 -0.75 (VIOLATED)
_079_/ZN 4.00 4.74 -0.74 (VIOLATED)
output19/I 4.00 4.69 -0.69 (VIOLATED)
ANTENNA_output19_I/I 4.00 4.69 -0.69 (VIOLATED)
_090_/A1 4.00 4.69 -0.69 (VIOLATED)
ANTENNA__090__A1/I 4.00 4.69 -0.69 (VIOLATED)
_123_/Q 4.00 4.68 -0.68 (VIOLATED)
output7/I 4.00 4.65 -0.65 (VIOLATED)
ANTENNA_output7_I/I 4.00 4.65 -0.65 (VIOLATED)
_106_/B 4.00 4.65 -0.65 (VIOLATED)
ANTENNA__106__B/I 4.00 4.65 -0.65 (VIOLATED)
_107_/A3 4.00 4.65 -0.65 (VIOLATED)
ANTENNA__107__A3/I 4.00 4.65 -0.65 (VIOLATED)
_130_/Q 4.00 4.64 -0.64 (VIOLATED)
output20/I 4.00 4.62 -0.62 (VIOLATED)
ANTENNA_output20_I/I 4.00 4.62 -0.62 (VIOLATED)
ANTENNA__092__I/I 4.00 4.62 -0.62 (VIOLATED)
_092_/I 4.00 4.62 -0.62 (VIOLATED)
ANTENNA__097__A1/I 4.00 4.62 -0.62 (VIOLATED)
_097_/A1 4.00 4.62 -0.62 (VIOLATED)
_124_/Q 4.00 4.61 -0.61 (VIOLATED)
_130_/D 4.00 4.46 -0.46 (VIOLATED)
ANTENNA__130__D/I 4.00 4.46 -0.46 (VIOLATED)
_109_/ZN 4.00 4.46 -0.46 (VIOLATED)
output5/I 4.00 4.44 -0.44 (VIOLATED)
ANTENNA_output5_I/I 4.00 4.44 -0.44 (VIOLATED)
_107_/A1 4.00 4.44 -0.44 (VIOLATED)
ANTENNA__107__A1/I 4.00 4.44 -0.44 (VIOLATED)
ANTENNA__102__I/I 4.00 4.44 -0.44 (VIOLATED)
_102_/I 4.00 4.44 -0.44 (VIOLATED)
_128_/Q 4.00 4.43 -0.43 (VIOLATED)
output3/I 4.00 4.40 -0.40 (VIOLATED)
ANTENNA_output3_I/I 4.00 4.40 -0.40 (VIOLATED)
ANTENNA__096__B/I 4.00 4.40 -0.40 (VIOLATED)
_096_/B 4.00 4.40 -0.40 (VIOLATED)
_097_/A3 4.00 4.40 -0.40 (VIOLATED)
ANTENNA__097__A3/I 4.00 4.40 -0.40 (VIOLATED)
_126_/Q 4.00 4.39 -0.39 (VIOLATED)
_131_/D 4.00 4.22 -0.22 (VIOLATED)
ANTENNA__131__D/I 4.00 4.22 -0.22 (VIOLATED)
_111_/ZN 4.00 4.22 -0.22 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
clkbuf_1_1__f_wb_clk_i/Z 4 18 -14 (VIOLATED)
clkbuf_1_0__f_wb_clk_i/Z 4 11 -7 (VIOLATED)
_056_/Z 4 8 -4 (VIOLATED)
_057_/Z 4 8 -4 (VIOLATED)
_061_/Z 4 8 -4 (VIOLATED)
_065_/Z 4 8 -4 (VIOLATED)
_072_/Z 4 8 -4 (VIOLATED)
_082_/Z 4 8 -4 (VIOLATED)
_092_/Z 4 8 -4 (VIOLATED)
_102_/Z 4 8 -4 (VIOLATED)
fanout22/Z 4 8 -4 (VIOLATED)
fanout23/Z 4 8 -4 (VIOLATED)
fanout24/Z 4 8 -4 (VIOLATED)
fanout25/Z 4 8 -4 (VIOLATED)
fanout26/Z 4 8 -4 (VIOLATED)
_112_/Q 4 6 -2 (VIOLATED)
_114_/Q 4 6 -2 (VIOLATED)
_116_/Q 4 6 -2 (VIOLATED)
_118_/Q 4 6 -2 (VIOLATED)
_120_/Q 4 6 -2 (VIOLATED)
_122_/Q 4 6 -2 (VIOLATED)
_124_/Q 4 6 -2 (VIOLATED)
_126_/Q 4 6 -2 (VIOLATED)
_128_/Q 4 6 -2 (VIOLATED)
_130_/Q 4 6 -2 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
_081_/ZN 0.13 0.35 -0.22 (VIOLATED)
_116_/Q 0.24 0.40 -0.16 (VIOLATED)
_120_/Q 0.24 0.38 -0.14 (VIOLATED)
_089_/ZN 0.13 0.27 -0.14 (VIOLATED)
_073_/ZN 0.13 0.26 -0.14 (VIOLATED)
_091_/ZN 0.13 0.25 -0.12 (VIOLATED)
_093_/ZN 0.13 0.25 -0.12 (VIOLATED)
_099_/ZN 0.13 0.25 -0.12 (VIOLATED)
_121_/Q 0.24 0.36 -0.12 (VIOLATED)
_071_/ZN 0.13 0.24 -0.11 (VIOLATED)
_085_/ZN 0.25 0.33 -0.09 (VIOLATED)
_118_/Q 0.24 0.31 -0.07 (VIOLATED)
_101_/ZN 0.13 0.20 -0.07 (VIOLATED)
_114_/Q 0.24 0.31 -0.07 (VIOLATED)
_083_/ZN 0.13 0.19 -0.06 (VIOLATED)
_103_/ZN 0.13 0.18 -0.06 (VIOLATED)
_060_/ZN 0.13 0.18 -0.05 (VIOLATED)
_123_/Q 0.24 0.29 -0.05 (VIOLATED)
_130_/Q 0.24 0.29 -0.05 (VIOLATED)
_068_/ZN 0.13 0.17 -0.05 (VIOLATED)
_124_/Q 0.24 0.29 -0.05 (VIOLATED)
_128_/Q 0.24 0.28 -0.04 (VIOLATED)
_079_/ZN 0.13 0.16 -0.04 (VIOLATED)
_126_/Q 0.24 0.27 -0.03 (VIOLATED)
_109_/ZN 0.13 0.15 -0.02 (VIOLATED)
_111_/ZN 0.13 0.14 -0.02 (VIOLATED)
======================= Fastest Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------
ANTENNA__119__D/I 2.60 6.33 -3.73 (VIOLATED)
_119_/D 2.60 6.33 -3.73 (VIOLATED)
_081_/ZN 2.60 6.32 -3.72 (VIOLATED)
ANTENNA__122__D/I 2.60 4.85 -2.25 (VIOLATED)
_122_/D 2.60 4.85 -2.25 (VIOLATED)
_089_/ZN 2.60 4.84 -2.24 (VIOLATED)
ANTENNA__116__D/I 2.60 4.83 -2.23 (VIOLATED)
_116_/D 2.60 4.83 -2.23 (VIOLATED)
_073_/ZN 2.60 4.82 -2.22 (VIOLATED)
ANTENNA__123__D/I 2.60 4.57 -1.97 (VIOLATED)
_123_/D 2.60 4.57 -1.97 (VIOLATED)
_091_/ZN 2.60 4.56 -1.96 (VIOLATED)
_124_/D 2.60 4.50 -1.90 (VIOLATED)
ANTENNA__124__D/I 2.60 4.50 -1.90 (VIOLATED)
_093_/ZN 2.60 4.49 -1.89 (VIOLATED)
_126_/D 2.60 4.49 -1.89 (VIOLATED)
ANTENNA__126__D/I 2.60 4.49 -1.89 (VIOLATED)
_099_/ZN 2.60 4.48 -1.88 (VIOLATED)
ANTENNA__115__D/I 2.60 4.36 -1.76 (VIOLATED)
_115_/D 2.60 4.36 -1.76 (VIOLATED)
_071_/ZN 2.60 4.35 -1.75 (VIOLATED)
output2/I 2.60 4.23 -1.63 (VIOLATED)
ANTENNA_output2_I/I 2.60 4.23 -1.63 (VIOLATED)
ANTENNA__072__I/I 2.60 4.23 -1.63 (VIOLATED)
_072_/I 2.60 4.23 -1.63 (VIOLATED)
ANTENNA__077__A1/I 2.60 4.23 -1.63 (VIOLATED)
_077_/A1 2.60 4.23 -1.63 (VIOLATED)
_116_/Q 2.60 4.21 -1.61 (VIOLATED)
output16/I 2.60 4.06 -1.46 (VIOLATED)
ANTENNA_output16_I/I 2.60 4.06 -1.46 (VIOLATED)
_082_/I 2.60 4.05 -1.45 (VIOLATED)
ANTENNA__082__I/I 2.60 4.05 -1.45 (VIOLATED)
_087_/A1 2.60 4.05 -1.45 (VIOLATED)
ANTENNA__087__A1/I 2.60 4.05 -1.45 (VIOLATED)
_120_/Q 2.60 4.03 -1.43 (VIOLATED)
_087_/A2 2.60 3.83 -1.23 (VIOLATED)
ANTENNA__087__A2/I 2.60 3.83 -1.23 (VIOLATED)
ANTENNA_fanout24_I/I 2.60 3.83 -1.23 (VIOLATED)
fanout24/I 2.60 3.83 -1.23 (VIOLATED)
_121_/Q 2.60 3.81 -1.21 (VIOLATED)
_127_/D 2.60 3.65 -1.05 (VIOLATED)
ANTENNA__127__D/I 2.60 3.65 -1.05 (VIOLATED)
_101_/ZN 2.60 3.65 -1.05 (VIOLATED)
ANTENNA__120__D/I 2.60 3.41 -0.81 (VIOLATED)
_120_/D 2.60 3.41 -0.81 (VIOLATED)
_083_/ZN 2.60 3.41 -0.81 (VIOLATED)
ANTENNA__128__D/I 2.60 3.37 -0.77 (VIOLATED)
_128_/D 2.60 3.37 -0.77 (VIOLATED)
_103_/ZN 2.60 3.36 -0.76 (VIOLATED)
output14/I 2.60 3.35 -0.75 (VIOLATED)
ANTENNA_output14_I/I 2.60 3.35 -0.75 (VIOLATED)
_076_/B 2.60 3.35 -0.75 (VIOLATED)
_077_/A3 2.60 3.35 -0.75 (VIOLATED)
ANTENNA__077__A3/I 2.60 3.35 -0.75 (VIOLATED)
ANTENNA__076__B/I 2.60 3.35 -0.75 (VIOLATED)
_118_/Q 2.60 3.33 -0.73 (VIOLATED)
ANTENNA__112__D/I 2.60 3.30 -0.70 (VIOLATED)
_112_/D 2.60 3.30 -0.70 (VIOLATED)
_060_/ZN 2.60 3.30 -0.70 (VIOLATED)
output11/I 2.60 3.26 -0.66 (VIOLATED)
ANTENNA_output11_I/I 2.60 3.26 -0.66 (VIOLATED)
_064_/B 2.60 3.26 -0.66 (VIOLATED)
ANTENNA__064__B/I 2.60 3.26 -0.66 (VIOLATED)
ANTENNA__066__A3/I 2.60 3.26 -0.66 (VIOLATED)
_066_/A3 2.60 3.26 -0.66 (VIOLATED)
_114_/Q 2.60 3.25 -0.65 (VIOLATED)
_114_/D 2.60 3.21 -0.61 (VIOLATED)
ANTENNA__114__D/I 2.60 3.21 -0.61 (VIOLATED)
_068_/ZN 2.60 3.21 -0.61 (VIOLATED)
output19/I 2.60 3.13 -0.53 (VIOLATED)
ANTENNA_output19_I/I 2.60 3.13 -0.53 (VIOLATED)
_090_/A1 2.60 3.13 -0.53 (VIOLATED)
ANTENNA__090__A1/I 2.60 3.13 -0.53 (VIOLATED)
_123_/Q 2.60 3.11 -0.51 (VIOLATED)
ANTENNA__121__D/I 2.60 3.11 -0.51 (VIOLATED)
_121_/D 2.60 3.11 -0.51 (VIOLATED)
output7/I 2.60 3.10 -0.50 (VIOLATED)
ANTENNA_output7_I/I 2.60 3.10 -0.50 (VIOLATED)
_106_/B 2.60 3.10 -0.50 (VIOLATED)
ANTENNA__106__B/I 2.60 3.10 -0.50 (VIOLATED)
_107_/A3 2.60 3.10 -0.50 (VIOLATED)
ANTENNA__107__A3/I 2.60 3.10 -0.50 (VIOLATED)
_085_/ZN 2.60 3.09 -0.49 (VIOLATED)
_130_/Q 2.60 3.08 -0.48 (VIOLATED)
output20/I 2.60 3.08 -0.48 (VIOLATED)
ANTENNA_output20_I/I 2.60 3.08 -0.48 (VIOLATED)
ANTENNA__092__I/I 2.60 3.08 -0.48 (VIOLATED)
_092_/I 2.60 3.08 -0.48 (VIOLATED)
ANTENNA__097__A1/I 2.60 3.08 -0.48 (VIOLATED)
_097_/A1 2.60 3.08 -0.48 (VIOLATED)
_124_/Q 2.60 3.06 -0.46 (VIOLATED)
output5/I 2.60 2.96 -0.36 (VIOLATED)
ANTENNA_output5_I/I 2.60 2.96 -0.36 (VIOLATED)
_107_/A1 2.60 2.96 -0.36 (VIOLATED)
ANTENNA__107__A1/I 2.60 2.96 -0.36 (VIOLATED)
ANTENNA__102__I/I 2.60 2.96 -0.36 (VIOLATED)
_102_/I 2.60 2.96 -0.36 (VIOLATED)
ANTENNA__118__D/I 2.60 2.96 -0.36 (VIOLATED)
_118_/D 2.60 2.96 -0.36 (VIOLATED)
_079_/ZN 2.60 2.95 -0.35 (VIOLATED)
_128_/Q 2.60 2.94 -0.34 (VIOLATED)
output3/I 2.60 2.93 -0.33 (VIOLATED)
ANTENNA_output3_I/I 2.60 2.93 -0.33 (VIOLATED)
ANTENNA__096__B/I 2.60 2.93 -0.33 (VIOLATED)
_096_/B 2.60 2.93 -0.33 (VIOLATED)
_097_/A3 2.60 2.93 -0.33 (VIOLATED)
ANTENNA__097__A3/I 2.60 2.93 -0.33 (VIOLATED)
_126_/Q 2.60 2.92 -0.32 (VIOLATED)
_130_/D 2.60 2.77 -0.17 (VIOLATED)
ANTENNA__130__D/I 2.60 2.77 -0.17 (VIOLATED)
_109_/ZN 2.60 2.77 -0.17 (VIOLATED)
_131_/D 2.60 2.62 -0.02 (VIOLATED)
ANTENNA__131__D/I 2.60 2.62 -0.02 (VIOLATED)
_111_/ZN 2.60 2.62 -0.02 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
clkbuf_1_1__f_wb_clk_i/Z 4 18 -14 (VIOLATED)
clkbuf_1_0__f_wb_clk_i/Z 4 11 -7 (VIOLATED)
_056_/Z 4 8 -4 (VIOLATED)
_057_/Z 4 8 -4 (VIOLATED)
_061_/Z 4 8 -4 (VIOLATED)
_065_/Z 4 8 -4 (VIOLATED)
_072_/Z 4 8 -4 (VIOLATED)
_082_/Z 4 8 -4 (VIOLATED)
_092_/Z 4 8 -4 (VIOLATED)
_102_/Z 4 8 -4 (VIOLATED)
fanout22/Z 4 8 -4 (VIOLATED)
fanout23/Z 4 8 -4 (VIOLATED)
fanout24/Z 4 8 -4 (VIOLATED)
fanout25/Z 4 8 -4 (VIOLATED)
fanout26/Z 4 8 -4 (VIOLATED)
_112_/Q 4 6 -2 (VIOLATED)
_114_/Q 4 6 -2 (VIOLATED)
_116_/Q 4 6 -2 (VIOLATED)
_118_/Q 4 6 -2 (VIOLATED)
_120_/Q 4 6 -2 (VIOLATED)
_122_/Q 4 6 -2 (VIOLATED)
_124_/Q 4 6 -2 (VIOLATED)
_126_/Q 4 6 -2 (VIOLATED)
_128_/Q 4 6 -2 (VIOLATED)
_130_/Q 4 6 -2 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
_081_/ZN 0.13 0.35 -0.22 (VIOLATED)
_116_/Q 0.23 0.40 -0.16 (VIOLATED)
_120_/Q 0.23 0.38 -0.15 (VIOLATED)
_089_/ZN 0.13 0.27 -0.14 (VIOLATED)
_073_/ZN 0.13 0.26 -0.13 (VIOLATED)
_121_/Q 0.23 0.36 -0.13 (VIOLATED)
_091_/ZN 0.13 0.25 -0.12 (VIOLATED)
_093_/ZN 0.13 0.25 -0.12 (VIOLATED)
_099_/ZN 0.13 0.25 -0.11 (VIOLATED)
_071_/ZN 0.13 0.24 -0.11 (VIOLATED)
_118_/Q 0.23 0.31 -0.08 (VIOLATED)
_085_/ZN 0.26 0.33 -0.08 (VIOLATED)
_114_/Q 0.23 0.31 -0.07 (VIOLATED)
_101_/ZN 0.13 0.20 -0.07 (VIOLATED)
_123_/Q 0.23 0.29 -0.06 (VIOLATED)
_130_/Q 0.23 0.29 -0.06 (VIOLATED)
_124_/Q 0.23 0.29 -0.06 (VIOLATED)
_083_/ZN 0.13 0.19 -0.05 (VIOLATED)
_103_/ZN 0.13 0.18 -0.05 (VIOLATED)
_060_/ZN 0.13 0.18 -0.05 (VIOLATED)
_068_/ZN 0.13 0.17 -0.04 (VIOLATED)
_128_/Q 0.23 0.28 -0.04 (VIOLATED)
_126_/Q 0.23 0.27 -0.04 (VIOLATED)
_079_/ZN 0.13 0.16 -0.03 (VIOLATED)
_109_/ZN 0.13 0.15 -0.02 (VIOLATED)
_111_/ZN 0.13 0.14 -0.01 (VIOLATED)
_113_/Q 0.23 0.24 -0.00 (VIOLATED)
===========================================================================
max slew violation count 114
max fanout violation count 25
max cap violation count 27
============================================================================
check_slew_end
tns_report
===========================================================================
report_tns
============================================================================
tns 0.00
tns_report_end
wns_report
===========================================================================
report_wns
============================================================================
wns 0.00
wns_report_end
worst_slack
===========================================================================
report_worst_slack -max (Setup)
============================================================================
worst slack 36.01
===========================================================================
report_worst_slack -min (Hold)
============================================================================
worst slack 2.34
worst_slack_end
clock_skew
===========================================================================
report_clock_skew
============================================================================
======================== Slowest Corner ==================================
Clock wb_clk_i
Latency CRPR Skew
_118_/CLK ^
1.09
_119_/CLK ^
0.97 -0.06 0.06
======================= Typical Corner ===================================
Clock wb_clk_i
Latency CRPR Skew
_118_/CLK ^
0.61
_119_/CLK ^
0.54 -0.03 0.03
======================= Fastest Corner ===================================
Clock wb_clk_i
Latency CRPR Skew
_118_/CLK ^
0.39
_119_/CLK ^
0.35 -0.02 0.02
clock_skew_end
power_report
===========================================================================
report_power
============================================================================
======================= Slowest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 1.40e-04 8.76e-05 1.16e-08 2.28e-04 37.7%
Combinational 1.64e-04 1.76e-04 3.68e-05 3.77e-04 62.3%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 3.04e-04 2.64e-04 3.68e-05 6.05e-04 100.0%
50.3% 43.7% 6.1%
======================= Typical Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 1.69e-04 1.08e-04 4.08e-09 2.77e-04 39.0%
Combinational 2.15e-04 2.16e-04 2.94e-06 4.34e-04 61.0%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 3.84e-04 3.24e-04 2.94e-06 7.12e-04 100.0%
54.0% 45.6% 0.4%
======================= Fastest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 2.07e-04 1.30e-04 4.86e-09 3.38e-04 38.0%
Combinational 2.87e-04 2.61e-04 3.55e-06 5.51e-04 62.0%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 4.94e-04 3.91e-04 3.56e-06 8.89e-04 100.0%
55.6% 44.0% 0.4%
power_report_end
area_report
===========================================================================
report_design_area
============================================================================
Design area 68361 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF files for all corners...
Writing SDF for the ff corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.ff.sdf...
Writing SDF for the ss corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.ss.sdf...
Writing SDF for the tt corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.tt.sdf...
Writing timing models for all corners...
Writing timing models for the ff corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.ff.lib...
Writing timing models for the ss corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.ss.lib...
Writing timing models for the tt corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/mca/process_corner_nom/cntr_example.tt.lib...