| OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ORD-0030] Using 2 thread(s). |
| [INFO DRT-0149] Reading tech and libs. |
| [WARNING DRT-0140] SpacingRange unsupported. |
| [WARNING DRT-0140] SpacingRange unsupported. |
| [WARNING DRT-0140] SpacingRange unsupported. |
| [WARNING DRT-0140] SpacingRange unsupported. |
| [WARNING DRT-0140] SpacingRange unsupported. |
| |
| Units: 2000 |
| Number of layers: 11 |
| Number of macros: 229 |
| Number of vias: 60 |
| Number of viarulegen: 18 |
| |
| [INFO DRT-0150] Reading design. |
| |
| Design: cntr_example |
| Die area: ( 0 0 ) ( 3000000 3000000 ) |
| Number of track patterns: 10 |
| Number of DEF vias: 3 |
| Number of components: 58381 |
| Number of terminals: 42 |
| Number of snets: 2 |
| Number of nets: 125 |
| |
| [INFO DRT-0167] List of default vias: |
| Layer Via1 |
| default via: Via1_HV |
| Layer Via2 |
| default via: Via2_VH |
| Layer Via3 |
| default via: Via3_HV |
| Layer Via4 |
| default via: Via4_1_VH |
| [INFO DRT-0162] Library cell analysis. |
| [INFO DRT-0163] Instance analysis. |
| Complete 10000 instances. |
| Complete 20000 instances. |
| Complete 30000 instances. |
| Complete 40000 instances. |
| Complete 50000 instances. |
| [INFO DRT-0164] Number of unique instances = 62. |
| [INFO DRT-0168] Init region query. |
| [INFO DRT-0018] Complete 10000 insts. |
| [INFO DRT-0018] Complete 20000 insts. |
| [INFO DRT-0018] Complete 30000 insts. |
| [INFO DRT-0018] Complete 40000 insts. |
| [INFO DRT-0018] Complete 50000 insts. |
| [INFO DRT-0024] Complete Poly2. |
| [INFO DRT-0024] Complete CON. |
| [INFO DRT-0024] Complete Metal1. |
| [INFO DRT-0024] Complete Via1. |
| [INFO DRT-0024] Complete Metal2. |
| [INFO DRT-0024] Complete Via2. |
| [INFO DRT-0024] Complete Metal3. |
| [INFO DRT-0024] Complete Via3. |
| [INFO DRT-0024] Complete Metal4. |
| [INFO DRT-0024] Complete Via4. |
| [INFO DRT-0024] Complete Metal5. |
| [INFO DRT-0033] Poly2 shape region query size = 0. |
| [INFO DRT-0033] CON shape region query size = 0. |
| [INFO DRT-0033] Metal1 shape region query size = 1571796. |
| [INFO DRT-0033] Via1 shape region query size = 11250. |
| [INFO DRT-0033] Metal2 shape region query size = 7540. |
| [INFO DRT-0033] Via2 shape region query size = 11250. |
| [INFO DRT-0033] Metal3 shape region query size = 7500. |
| [INFO DRT-0033] Via3 shape region query size = 11250. |
| [INFO DRT-0033] Metal4 shape region query size = 3790. |
| [INFO DRT-0033] Via4 shape region query size = 0. |
| [INFO DRT-0033] Metal5 shape region query size = 0. |
| [INFO DRT-0165] Start pin access. |
| [INFO DRT-0076] Complete 100 pins. |
| [INFO DRT-0078] Complete 116 pins. |
| [INFO DRT-0081] Complete 42 unique inst patterns. |
| [INFO DRT-0084] Complete 262 groups. |
| #scanned instances = 58381 |
| #unique instances = 62 |
| #stdCellGenAp = 689 |
| #stdCellValidPlanarAp = 0 |
| #stdCellValidViaAp = 610 |
| #stdCellPinNoAp = 0 |
| #stdCellPinCnt = 295 |
| #instTermValidViaApCnt = 0 |
| #macroGenAp = 0 |
| #macroValidPlanarAp = 0 |
| #macroValidViaAp = 0 |
| #macroNoAp = 0 |
| [INFO DRT-0166] Complete pin access. |
| [INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:01, memory = 325.20 (MB), peak = 360.11 (MB) |
| |
| Number of guides: 1031 |
| |
| [INFO DRT-0169] Post process guides. |
| [INFO DRT-0176] GCELLGRID X 0 DO 178 STEP 16800 ; |
| [INFO DRT-0177] GCELLGRID Y 0 DO 178 STEP 16800 ; |
| [INFO DRT-0028] Complete Poly2. |
| [INFO DRT-0028] Complete CON. |
| [INFO DRT-0028] Complete Metal1. |
| [INFO DRT-0028] Complete Via1. |
| [INFO DRT-0028] Complete Metal2. |
| [INFO DRT-0028] Complete Via2. |
| [INFO DRT-0028] Complete Metal3. |
| [INFO DRT-0028] Complete Via3. |
| [INFO DRT-0028] Complete Metal4. |
| [INFO DRT-0028] Complete Via4. |
| [INFO DRT-0028] Complete Metal5. |
| [INFO DRT-0178] Init guide query. |
| [INFO DRT-0035] Complete Poly2 (guide). |
| [INFO DRT-0035] Complete CON (guide). |
| [INFO DRT-0035] Complete Metal1 (guide). |
| [INFO DRT-0035] Complete Via1 (guide). |
| [INFO DRT-0035] Complete Metal2 (guide). |
| [INFO DRT-0035] Complete Via2 (guide). |
| [INFO DRT-0035] Complete Metal3 (guide). |
| [INFO DRT-0035] Complete Via3 (guide). |
| [INFO DRT-0035] Complete Metal4 (guide). |
| [INFO DRT-0035] Complete Via4 (guide). |
| [INFO DRT-0035] Complete Metal5 (guide). |
| [INFO DRT-0036] Poly2 guide region query size = 0. |
| [INFO DRT-0036] CON guide region query size = 0. |
| [INFO DRT-0036] Metal1 guide region query size = 358. |
| [INFO DRT-0036] Via1 guide region query size = 0. |
| [INFO DRT-0036] Metal2 guide region query size = 353. |
| [INFO DRT-0036] Via2 guide region query size = 0. |
| [INFO DRT-0036] Metal3 guide region query size = 183. |
| [INFO DRT-0036] Via3 guide region query size = 0. |
| [INFO DRT-0036] Metal4 guide region query size = 3. |
| [INFO DRT-0036] Via4 guide region query size = 0. |
| [INFO DRT-0036] Metal5 guide region query size = 0. |
| [INFO DRT-0179] Init gr pin query. |
| [INFO DRT-0245] skipped writing guide updates to database. |
| [INFO DRT-0185] Post process initialize RPin region query. |
| [INFO DRT-0181] Start track assignment. |
| [INFO DRT-0184] Done with 356 vertical wires in 4 frboxes and 541 horizontal wires in 4 frboxes. |
| [INFO DRT-0186] Done with 62 vertical wires in 4 frboxes and 67 horizontal wires in 4 frboxes. |
| [INFO DRT-0182] Complete track assignment. |
| [INFO DRT-0267] cpu time = 00:00:05, elapsed time = 00:00:02, memory = 413.27 (MB), peak = 629.69 (MB) |
| [INFO DRT-0187] Start routing data preparation. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 413.27 (MB), peak = 629.69 (MB) |
| [INFO DRT-0194] Start detail routing. |
| [INFO DRT-0195] Start 0th optimization iteration. |
| Completing 10% with 0 violations. |
| elapsed time = 00:00:01, memory = 770.51 (MB). |
| Completing 20% with 0 violations. |
| elapsed time = 00:00:02, memory = 1249.58 (MB). |
| Completing 30% with 4 violations. |
| elapsed time = 00:00:04, memory = 1015.99 (MB). |
| Completing 40% with 4 violations. |
| elapsed time = 00:00:05, memory = 1241.68 (MB). |
| Completing 50% with 4 violations. |
| elapsed time = 00:00:06, memory = 1448.73 (MB). |
| Completing 60% with 13 violations. |
| elapsed time = 00:00:08, memory = 1449.80 (MB). |
| Completing 70% with 13 violations. |
| elapsed time = 00:00:09, memory = 1450.93 (MB). |
| Completing 80% with 16 violations. |
| elapsed time = 00:00:10, memory = 1470.09 (MB). |
| Completing 90% with 16 violations. |
| elapsed time = 00:00:11, memory = 1470.34 (MB). |
| Completing 100% with 16 violations. |
| elapsed time = 00:00:13, memory = 1101.24 (MB). |
| [INFO DRT-0199] Number of violations = 22. |
| Viol/Layer Metal2 Metal3 |
| Metal Spacing 3 0 |
| Recheck 5 1 |
| Short 13 0 |
| [INFO DRT-0267] cpu time = 00:00:24, elapsed time = 00:00:13, memory = 1101.24 (MB), peak = 1476.29 (MB) |
| Total wire length = 64956 um. |
| Total wire length on LAYER Metal1 = 61 um. |
| Total wire length on LAYER Metal2 = 54982 um. |
| Total wire length on LAYER Metal3 = 5818 um. |
| Total wire length on LAYER Metal4 = 4094 um. |
| Total wire length on LAYER Metal5 = 0 um. |
| Total number of vias = 951. |
| Up-via summary (total 951):. |
| |
| -------------- |
| Poly2 0 |
| Metal1 482 |
| Metal2 463 |
| Metal3 6 |
| Metal4 0 |
| -------------- |
| 951 |
| |
| |
| [INFO DRT-0195] Start 1st optimization iteration. |
| Completing 10% with 22 violations. |
| elapsed time = 00:00:01, memory = 1137.14 (MB). |
| Completing 20% with 22 violations. |
| elapsed time = 00:00:02, memory = 1343.91 (MB). |
| Completing 30% with 17 violations. |
| elapsed time = 00:00:03, memory = 1008.66 (MB). |
| Completing 40% with 17 violations. |
| elapsed time = 00:00:05, memory = 1220.41 (MB). |
| Completing 50% with 17 violations. |
| elapsed time = 00:00:06, memory = 1443.15 (MB). |
| Completing 60% with 7 violations. |
| elapsed time = 00:00:08, memory = 1151.66 (MB). |
| Completing 70% with 7 violations. |
| elapsed time = 00:00:09, memory = 1374.15 (MB). |
| Completing 80% with 4 violations. |
| elapsed time = 00:00:10, memory = 1466.71 (MB). |
| Completing 90% with 4 violations. |
| elapsed time = 00:00:12, memory = 1468.00 (MB). |
| Completing 100% with 6 violations. |
| elapsed time = 00:00:13, memory = 1475.79 (MB). |
| [INFO DRT-0199] Number of violations = 6. |
| Viol/Layer Metal2 |
| Metal Spacing 1 |
| Short 5 |
| [INFO DRT-0267] cpu time = 00:00:25, elapsed time = 00:00:13, memory = 909.44 (MB), peak = 1476.29 (MB) |
| Total wire length = 64921 um. |
| Total wire length on LAYER Metal1 = 60 um. |
| Total wire length on LAYER Metal2 = 54925 um. |
| Total wire length on LAYER Metal3 = 5840 um. |
| Total wire length on LAYER Metal4 = 4095 um. |
| Total wire length on LAYER Metal5 = 0 um. |
| Total number of vias = 966. |
| Up-via summary (total 966):. |
| |
| -------------- |
| Poly2 0 |
| Metal1 482 |
| Metal2 478 |
| Metal3 6 |
| Metal4 0 |
| -------------- |
| 966 |
| |
| |
| [INFO DRT-0195] Start 2nd optimization iteration. |
| Completing 10% with 6 violations. |
| elapsed time = 00:00:00, memory = 909.44 (MB). |
| Completing 20% with 6 violations. |
| elapsed time = 00:00:00, memory = 909.44 (MB). |
| Completing 30% with 6 violations. |
| elapsed time = 00:00:00, memory = 909.44 (MB). |
| Completing 40% with 6 violations. |
| elapsed time = 00:00:00, memory = 909.58 (MB). |
| Completing 50% with 6 violations. |
| elapsed time = 00:00:00, memory = 909.58 (MB). |
| Completing 60% with 6 violations. |
| elapsed time = 00:00:00, memory = 918.60 (MB). |
| Completing 70% with 6 violations. |
| elapsed time = 00:00:00, memory = 918.61 (MB). |
| Completing 80% with 5 violations. |
| elapsed time = 00:00:00, memory = 918.61 (MB). |
| Completing 90% with 5 violations. |
| elapsed time = 00:00:00, memory = 919.12 (MB). |
| Completing 100% with 5 violations. |
| elapsed time = 00:00:00, memory = 919.14 (MB). |
| [INFO DRT-0199] Number of violations = 5. |
| Viol/Layer Metal2 |
| Metal Spacing 1 |
| Short 4 |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 919.14 (MB), peak = 1476.29 (MB) |
| Total wire length = 64903 um. |
| Total wire length on LAYER Metal1 = 60 um. |
| Total wire length on LAYER Metal2 = 54943 um. |
| Total wire length on LAYER Metal3 = 5804 um. |
| Total wire length on LAYER Metal4 = 4095 um. |
| Total wire length on LAYER Metal5 = 0 um. |
| Total number of vias = 951. |
| Up-via summary (total 951):. |
| |
| -------------- |
| Poly2 0 |
| Metal1 478 |
| Metal2 467 |
| Metal3 6 |
| Metal4 0 |
| -------------- |
| 951 |
| |
| |
| [INFO DRT-0195] Start 3rd optimization iteration. |
| Completing 10% with 5 violations. |
| elapsed time = 00:00:00, memory = 919.14 (MB). |
| Completing 20% with 5 violations. |
| elapsed time = 00:00:00, memory = 919.14 (MB). |
| Completing 30% with 3 violations. |
| elapsed time = 00:00:00, memory = 921.45 (MB). |
| Completing 40% with 3 violations. |
| elapsed time = 00:00:00, memory = 921.46 (MB). |
| Completing 50% with 3 violations. |
| elapsed time = 00:00:00, memory = 921.46 (MB). |
| Completing 60% with 0 violations. |
| elapsed time = 00:00:00, memory = 921.46 (MB). |
| Completing 70% with 0 violations. |
| elapsed time = 00:00:00, memory = 921.46 (MB). |
| Completing 80% with 0 violations. |
| elapsed time = 00:00:00, memory = 921.46 (MB). |
| Completing 90% with 0 violations. |
| elapsed time = 00:00:00, memory = 921.46 (MB). |
| Completing 100% with 0 violations. |
| elapsed time = 00:00:00, memory = 921.46 (MB). |
| [INFO DRT-0199] Number of violations = 0. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 921.46 (MB), peak = 1476.29 (MB) |
| Total wire length = 64901 um. |
| Total wire length on LAYER Metal1 = 60 um. |
| Total wire length on LAYER Metal2 = 54829 um. |
| Total wire length on LAYER Metal3 = 5810 um. |
| Total wire length on LAYER Metal4 = 4201 um. |
| Total wire length on LAYER Metal5 = 0 um. |
| Total number of vias = 969. |
| Up-via summary (total 969):. |
| |
| -------------- |
| Poly2 0 |
| Metal1 478 |
| Metal2 476 |
| Metal3 15 |
| Metal4 0 |
| -------------- |
| 969 |
| |
| |
| [INFO DRT-0198] Complete detail routing. |
| Total wire length = 64901 um. |
| Total wire length on LAYER Metal1 = 60 um. |
| Total wire length on LAYER Metal2 = 54829 um. |
| Total wire length on LAYER Metal3 = 5810 um. |
| Total wire length on LAYER Metal4 = 4201 um. |
| Total wire length on LAYER Metal5 = 0 um. |
| Total number of vias = 969. |
| Up-via summary (total 969):. |
| |
| -------------- |
| Poly2 0 |
| Metal1 478 |
| Metal2 476 |
| Metal3 15 |
| Metal4 0 |
| -------------- |
| 969 |
| |
| |
| [INFO DRT-0267] cpu time = 00:00:51, elapsed time = 00:00:27, memory = 921.46 (MB), peak = 1476.29 (MB) |
| |
| [INFO DRT-0180] Post processing. |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/cntr_example.odb... |
| Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/cntr_example.nl.v... |
| Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/cntr_example.pnl.v... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/results/routing/cntr_example.def... |
