| OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2. |
| [INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4. |
| -congestion_iterations 50 -verbose |
| [INFO GRT-0020] Min routing layer: Metal2 |
| [INFO GRT-0021] Max routing layer: Metal4 |
| [INFO GRT-0022] Global adjustment: 30% |
| [INFO GRT-0023] Grid origin: (0, 0) |
| [INFO GRT-0043] No OR_DEFAULT vias defined. |
| [INFO GRT-0088] Layer Metal1 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5450 |
| [INFO GRT-0088] Layer Metal2 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800 |
| [INFO GRT-0088] Layer Metal3 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800 |
| [INFO GRT-0088] Layer Metal4 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800 |
| [INFO GRT-0019] Found 4 clock nets. |
| [INFO GRT-0001] Minimum degree: 2 |
| [INFO GRT-0002] Maximum degree: 19 |
| [INFO GRT-0003] Macros: 0 |
| [INFO GRT-0004] Blockages: 0 |
| |
| [INFO GRT-0053] Routing resources analysis: |
| Routing Original Derated Resource |
| Layer Direction Resources Resources Reduction (%) |
| --------------------------------------------------------------- |
| Metal1 Horizontal 0 0 0.00% |
| Metal2 Vertical 443576 286032 35.52% |
| Metal3 Horizontal 443576 286032 35.52% |
| Metal4 Vertical 443576 283057 36.19% |
| --------------------------------------------------------------- |
| |
| [INFO GRT-0197] Via related to pin nodes: 632 |
| [INFO GRT-0198] Via related Steiner nodes: 13 |
| [INFO GRT-0199] Via filling finished. |
| [INFO GRT-0111] Final number of vias: 744 |
| [INFO GRT-0112] Final usage 3D: 9910 |
| |
| [INFO GRT-0096] Final congestion report: |
| Layer Resource Demand Usage (%) Max H / Max V / Total Overflow |
| --------------------------------------------------------------------------------------- |
| Metal1 0 0 0.00% 0 / 0 / 0 |
| Metal2 286032 6486 2.27% 0 / 0 / 0 |
| Metal3 286032 705 0.25% 0 / 0 / 0 |
| Metal4 283057 487 0.17% 0 / 0 / 0 |
| --------------------------------------------------------------------------------------- |
| Total 855121 7678 0.90% 0 / 0 / 0 |
| |
| [INFO GRT-0018] Total wirelength: 68838 um |
| [INFO GRT-0014] Routed nets: 125 |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/routing/16-global.odb... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/routing/16-global.def... |
| Writing routing guides to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/routing/16-global.guide... |
| [INFO]: Setting RC values... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.52 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.52 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.36 0.79 1.31 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.03 net3 (net) |
| 0.36 0.01 1.32 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.55 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _046_ (net) |
| 0.27 0.00 1.55 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.79 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.02 _014_ (net) |
| 0.30 0.00 1.79 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.79 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.58 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.83 clock uncertainty |
| -0.06 0.77 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.79 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.99 slack (MET) |
| |
| |
| Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.52 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.52 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.37 0.79 1.32 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.03 net18 (net) |
| 0.37 0.01 1.33 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.55 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _040_ (net) |
| 0.27 0.00 1.55 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.79 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.02 _010_ (net) |
| 0.30 0.00 1.80 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.80 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.58 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.83 clock uncertainty |
| -0.06 0.77 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.80 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.99 slack (MET) |
| |
| |
| Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 0.52 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.52 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.38 0.80 1.33 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.04 net14 (net) |
| 0.38 0.01 1.34 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.28 0.23 1.57 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _034_ (net) |
| 0.28 0.00 1.57 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.81 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.02 _006_ (net) |
| 0.30 0.00 1.81 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.81 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.58 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.83 clock uncertainty |
| -0.06 0.77 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.81 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.01 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.23 0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.52 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.38 0.80 1.32 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.04 net7 (net) |
| 0.38 0.01 1.33 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.28 0.23 1.56 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _052_ (net) |
| 0.28 0.00 1.56 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.31 0.25 1.81 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.02 _018_ (net) |
| 0.31 0.01 1.82 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.82 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.58 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.83 clock uncertainty |
| -0.05 0.77 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.02 slack (MET) |
| |
| |
| Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.23 0.52 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.52 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.35 0.78 1.30 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.03 net4 (net) |
| 0.35 0.01 1.31 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.28 0.24 1.55 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.00 _049_ (net) |
| 0.28 0.00 1.55 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.31 0.26 1.81 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.02 _015_ (net) |
| 0.31 0.00 1.82 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.82 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.58 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 0.83 clock uncertainty |
| -0.05 0.77 clock reconvergence pessimism |
| 0.03 0.80 library hold time |
| 0.80 data required time |
| ----------------------------------------------------------------------------- |
| 0.80 data required time |
| -1.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.02 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[1] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.58 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.44 0.96 1.54 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.02 net13 (net) |
| 0.44 0.01 1.54 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.60 0.55 2.10 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.03 net25 (net) |
| 0.60 0.00 2.10 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.34 0.53 2.62 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_out[1] (net) |
| 0.34 0.00 2.63 ^ io_out[1] (out) |
| 2.63 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.63 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.12 slack (MET) |
| |
| |
| Startpoint: _121_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[5] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.58 ^ _121_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.44 0.96 1.53 ^ _121_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.02 net17 (net) |
| 0.44 0.01 1.54 ^ fanout24/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.57 0.54 2.08 ^ fanout24/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.03 net24 (net) |
| 0.57 0.00 2.08 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.34 0.52 2.60 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_out[5] (net) |
| 0.34 0.00 2.60 ^ io_out[5] (out) |
| 2.60 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.60 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.15 slack (MET) |
| |
| |
| Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[18] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.58 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.64 1.07 1.65 ^ _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.04 net11 (net) |
| 0.64 0.02 1.66 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.34 0.53 2.20 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_out[18] (net) |
| 0.34 0.00 2.20 ^ io_out[18] (out) |
| 2.20 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.20 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.55 slack (MET) |
| |
| |
| Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[2] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.58 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.62 1.06 1.64 ^ _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.04 net14 (net) |
| 0.63 0.01 1.66 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.34 0.53 2.19 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_out[2] (net) |
| 0.34 0.00 2.19 ^ io_out[2] (out) |
| 2.19 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.19 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.56 slack (MET) |
| |
| |
| Startpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[0] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.10 0.25 0.57 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.10 0.00 0.58 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.62 1.06 1.64 ^ _116_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.04 net2 (net) |
| 0.62 0.01 1.65 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.34 0.53 2.18 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_out[0] (net) |
| 0.34 0.00 2.18 ^ io_out[0] (out) |
| 2.18 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.18 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.57 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: _117_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[1] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.25 0.58 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.11 0.00 0.58 ^ _117_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.44 0.96 1.54 ^ _117_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.02 net13 (net) |
| 0.44 0.01 1.54 ^ fanout25/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.60 0.55 2.10 ^ fanout25/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.03 net25 (net) |
| 0.60 0.00 2.10 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.34 0.53 2.62 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_out[1] (net) |
| 0.34 0.00 2.63 ^ io_out[1] (out) |
| 2.63 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.63 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.12 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| max fanout |
| |
| Pin Limit Fanout Slack |
| --------------------------------------------------------- |
| clkbuf_1_1__f_wb_clk_i/Z 4 18 -14 (VIOLATED) |
| clkbuf_1_0__f_wb_clk_i/Z 4 11 -7 (VIOLATED) |
| _056_/Z 4 8 -4 (VIOLATED) |
| _057_/Z 4 8 -4 (VIOLATED) |
| _061_/Z 4 8 -4 (VIOLATED) |
| _065_/Z 4 8 -4 (VIOLATED) |
| _072_/Z 4 8 -4 (VIOLATED) |
| _082_/Z 4 8 -4 (VIOLATED) |
| _092_/Z 4 8 -4 (VIOLATED) |
| _102_/Z 4 8 -4 (VIOLATED) |
| fanout22/Z 4 8 -4 (VIOLATED) |
| fanout23/Z 4 8 -4 (VIOLATED) |
| fanout24/Z 4 8 -4 (VIOLATED) |
| fanout25/Z 4 8 -4 (VIOLATED) |
| fanout26/Z 4 8 -4 (VIOLATED) |
| _112_/Q 4 6 -2 (VIOLATED) |
| _114_/Q 4 6 -2 (VIOLATED) |
| _116_/Q 4 6 -2 (VIOLATED) |
| _118_/Q 4 6 -2 (VIOLATED) |
| _120_/Q 4 6 -2 (VIOLATED) |
| _122_/Q 4 6 -2 (VIOLATED) |
| _124_/Q 4 6 -2 (VIOLATED) |
| _126_/Q 4 6 -2 (VIOLATED) |
| _128_/Q 4 6 -2 (VIOLATED) |
| _130_/Q 4 6 -2 (VIOLATED) |
| |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 25 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 49.12 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 0.99 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _128_/CLK ^ |
| 0.58 |
| _130_/CLK ^ |
| 0.52 -0.03 0.03 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 1.66e-04 1.33e-05 4.08e-09 1.79e-04 38.4% |
| Combinational 1.84e-04 1.01e-04 2.94e-06 2.88e-04 61.6% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 3.50e-04 1.14e-04 2.94e-06 4.67e-04 100.0% |
| 74.9% 24.4% 0.6% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 68361 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/routing/16-global.odb... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/routing/16-global.def... |
| Writing routing guides to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/routing/16-global.guide... |
