| OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO]: Setting RC values... |
| [INFO RSZ-0027] Inserted 1 input buffers. |
| [INFO RSZ-0028] Inserted 20 output buffers. |
| [INFO RSZ-0058] Using max wire length 18670um. |
| [INFO RSZ-0035] Found 5 fanout violations. |
| [INFO RSZ-0038] Inserted 5 buffers in 5 nets. |
| [INFO RSZ-0039] Resized 41 instances. |
| [INFO RSZ-0042] Inserted 18 tie gf180mcu_fd_sc_mcu7t5v0__tiel instances. |
| Placement Analysis |
| --------------------------------- |
| total displacement 386.4 u |
| average displacement 0.0 u |
| max displacement 8.8 u |
| original HPWL 64083.2 u |
| legalized HPWL 64322.0 u |
| delta HPWL 0 % |
| |
| [INFO DPL-0020] Mirrored 64 instances |
| [INFO DPL-0021] HPWL before 64322.0 u |
| [INFO DPL-0022] HPWL after 64121.4 u |
| [INFO DPL-0023] HPWL delta -0.3 % |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.odb... |
| Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.nl.v... |
| Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.pnl.v... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.def... |
| Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.sdc... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.33 0.78 0.78 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net3 (net) |
| 0.33 0.01 0.79 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.26 0.22 1.00 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _046_ (net) |
| 0.26 0.00 1.00 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.23 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _014_ (net) |
| 0.29 0.00 1.23 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.23 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.23 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.94 slack (MET) |
| |
| |
| Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.34 0.78 0.78 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net18 (net) |
| 0.34 0.01 0.79 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.01 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _040_ (net) |
| 0.27 0.00 1.01 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.24 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _010_ (net) |
| 0.29 0.00 1.24 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.24 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.24 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.95 slack (MET) |
| |
| |
| Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.35 0.79 0.79 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net14 (net) |
| 0.35 0.01 0.80 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.03 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _034_ (net) |
| 0.27 0.00 1.03 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.25 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _006_ (net) |
| 0.29 0.00 1.26 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.26 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.26 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.97 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.34 0.79 0.79 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 net7 (net) |
| 0.34 0.01 0.80 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.22 1.02 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _052_ (net) |
| 0.27 0.00 1.02 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.26 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _018_ (net) |
| 0.30 0.00 1.26 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.26 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.26 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.97 slack (MET) |
| |
| |
| Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.32 0.78 0.78 v _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2 0.03 net4 (net) |
| 0.33 0.01 0.79 v _100_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.28 0.23 1.02 ^ _100_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.00 _049_ (net) |
| 0.28 0.00 1.02 ^ _101_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.25 1.27 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _015_ (net) |
| 0.29 0.00 1.27 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.27 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.27 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.98 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.11 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.11 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 0.28 0.36 13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2 0.03 net1 (net) |
| 0.28 0.01 13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.35 0.38 13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _021_ (net) |
| 0.35 0.00 13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.33 0.29 14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.33 0.00 14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.33 0.41 14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.33 0.00 14.49 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.61 0.46 14.95 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _007_ (net) |
| 0.61 0.00 14.95 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.95 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.95 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.55 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _123_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.11 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.11 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 0.28 0.36 13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2 0.03 net1 (net) |
| 0.28 0.01 13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.35 0.38 13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _021_ (net) |
| 0.35 0.00 13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.33 0.29 14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.33 0.00 14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.33 0.41 14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.33 0.00 14.49 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.61 0.46 14.95 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _011_ (net) |
| 0.61 0.00 14.95 ^ _123_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.95 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _123_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.95 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.55 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _115_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.11 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.11 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 0.28 0.36 13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2 0.03 net1 (net) |
| 0.28 0.01 13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.35 0.38 13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _021_ (net) |
| 0.35 0.00 13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.33 0.29 14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.33 0.00 14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.33 0.41 14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.33 0.00 14.49 v _071_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.61 0.45 14.94 ^ _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _003_ (net) |
| 0.61 0.00 14.95 ^ _115_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.95 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _115_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.95 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.55 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.11 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.11 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 0.28 0.36 13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2 0.03 net1 (net) |
| 0.28 0.01 13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.35 0.38 13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _021_ (net) |
| 0.35 0.00 13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.33 0.29 14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.33 0.00 14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.33 0.41 14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.33 0.00 14.49 v _103_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.61 0.45 14.94 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _016_ (net) |
| 0.61 0.00 14.95 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.95 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.95 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.55 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.11 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.11 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 0.28 0.36 13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2 0.03 net1 (net) |
| 0.28 0.01 13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.35 0.38 13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _021_ (net) |
| 0.35 0.00 13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.33 0.29 14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.33 0.00 14.08 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.31 0.40 14.48 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _023_ (net) |
| 0.31 0.00 14.48 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.62 0.46 14.94 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _004_ (net) |
| 0.62 0.00 14.94 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.94 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.94 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.56 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.11 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.11 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 0.28 0.36 13.40 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_2) |
| 2 0.03 net1 (net) |
| 0.28 0.01 13.42 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.35 0.38 13.80 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _021_ (net) |
| 0.35 0.00 13.80 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.33 0.29 14.08 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.33 0.00 14.08 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.33 0.41 14.49 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.02 _030_ (net) |
| 0.33 0.00 14.49 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.61 0.46 14.95 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _007_ (net) |
| 0.61 0.00 14.95 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.95 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.95 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.55 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 49.55 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 0.94 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _112_/CLK ^ |
| 0.16 |
| _112_/CLK ^ |
| 0.15 0.00 0.02 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 1.67e-04 1.20e-05 4.08e-09 1.79e-04 68.5% |
| Combinational 3.03e-05 5.11e-05 7.45e-07 8.22e-05 31.5% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 1.97e-04 6.32e-05 7.49e-07 2.61e-04 100.0% |
| 75.5% 24.2% 0.3% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 67421 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.odb... |
| Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.nl.v... |
| Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.pnl.v... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.def... |
| Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/8-resizer.sdc... |
