| OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO]: Setting RC values... |
| [INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2. |
| [INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4. |
| [INFO GPL-0002] DBU: 2000 |
| [INFO GPL-0003] SiteSize: 1120 7840 |
| [INFO GPL-0004] CoreAreaLxLy: 13440 31360 |
| [INFO GPL-0005] CoreAreaUxUy: 2985920 2963520 |
| [INFO GPL-0006] NumInstances: 14008 |
| [INFO GPL-0007] NumPlaceInstances: 94 |
| [INFO GPL-0008] NumFixedInstances: 13914 |
| [INFO GPL-0009] NumDummyInstances: 0 |
| [INFO GPL-0010] NumNets: 96 |
| [INFO GPL-0011] NumPins: 295 |
| [INFO GPL-0012] DieAreaLxLy: 0 0 |
| [INFO GPL-0013] DieAreaUxUy: 3000000 3000000 |
| [INFO GPL-0014] CoreAreaLxLy: 13440 31360 |
| [INFO GPL-0015] CoreAreaUxUy: 2985920 2963520 |
| [INFO GPL-0016] CoreArea: 8715786956800 |
| [INFO GPL-0017] NonPlaceInstsArea: 244352102400 |
| [INFO GPL-0018] PlaceInstsArea: 9184716800 |
| [INFO GPL-0019] Util(%): 0.11 |
| [INFO GPL-0020] StdInstsArea: 9184716800 |
| [INFO GPL-0021] MacroInstsArea: 0 |
| [InitialPlace] Iter: 1 CG residual: 0.00025984 HPWL: 175440160 |
| [InitialPlace] Iter: 2 CG residual: 0.00000009 HPWL: 25812433 |
| [InitialPlace] Iter: 3 CG residual: 0.00000007 HPWL: 20280179 |
| [InitialPlace] Iter: 4 CG residual: 0.00000010 HPWL: 19219392 |
| [InitialPlace] Iter: 5 CG residual: 0.00000011 HPWL: 18703490 |
| [INFO GPL-0031] FillerInit: NumGCells: 41691 |
| [INFO GPL-0032] FillerInit: NumGNets: 96 |
| [INFO GPL-0033] FillerInit: NumGPins: 295 |
| [INFO GPL-0023] TargetDensity: 0.45 |
| [INFO GPL-0024] AveragePlaceInstArea: 97709753 |
| [INFO GPL-0025] IdealBinArea: 217132784 |
| [INFO GPL-0026] IdealBinCnt: 40140 |
| [INFO GPL-0027] TotalBinArea: 8715786956800 |
| [INFO GPL-0028] BinCnt: 128 128 |
| [INFO GPL-0029] BinSize: 23223 22908 |
| [INFO GPL-0030] NumBins: 16384 |
| [NesterovSolve] Iter: 1 overflow: 0.528129 HPWL: 18580576 |
| [INFO GPL-0100] worst slack 4.99e-08 |
| [INFO GPL-0103] Weighted 26 nets. |
| [NesterovSolve] Snapshot saved at iter = 0 |
| [INFO GPL-0100] worst slack 4.99e-08 |
| [INFO GPL-0103] Weighted 26 nets. |
| [INFO GPL-0100] worst slack 4.99e-08 |
| [INFO GPL-0103] Weighted 26 nets. |
| [NesterovSolve] Iter: 10 overflow: 0.301631 HPWL: 26749845 |
| [NesterovSolve] Iter: 20 overflow: 0.398354 HPWL: 29357513 |
| [NesterovSolve] Iter: 30 overflow: 0.464115 HPWL: 32791265 |
| [NesterovSolve] Iter: 40 overflow: 0.506961 HPWL: 40154131 |
| [NesterovSolve] Iter: 50 overflow: 0.482678 HPWL: 48610653 |
| [NesterovSolve] Iter: 60 overflow: 0.489071 HPWL: 57770056 |
| [NesterovSolve] Iter: 70 overflow: 0.478646 HPWL: 67899173 |
| [NesterovSolve] Iter: 80 overflow: 0.474213 HPWL: 78915214 |
| [NesterovSolve] Iter: 90 overflow: 0.406409 HPWL: 91006408 |
| [NesterovSolve] Iter: 100 overflow: 0.429896 HPWL: 103654765 |
| [NesterovSolve] Iter: 110 overflow: 0.474391 HPWL: 116990839 |
| [NesterovSolve] Iter: 120 overflow: 0.480198 HPWL: 132452568 |
| [NesterovSolve] Iter: 130 overflow: 0.47371 HPWL: 137422200 |
| [NesterovSolve] Iter: 140 overflow: 0.44902 HPWL: 137398151 |
| [NesterovSolve] Iter: 150 overflow: 0.442074 HPWL: 137371112 |
| [NesterovSolve] Iter: 160 overflow: 0.44857 HPWL: 137311345 |
| [NesterovSolve] Iter: 170 overflow: 0.451974 HPWL: 137212426 |
| [NesterovSolve] Iter: 180 overflow: 0.442524 HPWL: 137069489 |
| [NesterovSolve] Iter: 190 overflow: 0.432274 HPWL: 136901149 |
| [NesterovSolve] Iter: 200 overflow: 0.428708 HPWL: 136724437 |
| [NesterovSolve] Iter: 210 overflow: 0.429745 HPWL: 136553247 |
| [NesterovSolve] Iter: 220 overflow: 0.425941 HPWL: 136393345 |
| [NesterovSolve] Iter: 230 overflow: 0.417932 HPWL: 136244901 |
| [NesterovSolve] Iter: 240 overflow: 0.411437 HPWL: 136103046 |
| [NesterovSolve] Iter: 250 overflow: 0.414799 HPWL: 135957447 |
| [NesterovSolve] Iter: 260 overflow: 0.423075 HPWL: 135796810 |
| [NesterovSolve] Iter: 270 overflow: 0.43087 HPWL: 135614388 |
| [NesterovSolve] Iter: 280 overflow: 0.42859 HPWL: 135411341 |
| [NesterovSolve] Iter: 290 overflow: 0.423272 HPWL: 135195230 |
| [NesterovSolve] Iter: 300 overflow: 0.418159 HPWL: 134978816 |
| [NesterovSolve] Iter: 310 overflow: 0.410703 HPWL: 134771275 |
| [NesterovSolve] Iter: 320 overflow: 0.409016 HPWL: 134579694 |
| [NesterovSolve] Iter: 330 overflow: 0.410998 HPWL: 134400736 |
| [NesterovSolve] Iter: 340 overflow: 0.416172 HPWL: 134223914 |
| [NesterovSolve] Iter: 350 overflow: 0.418887 HPWL: 134042567 |
| [NesterovSolve] Iter: 360 overflow: 0.417121 HPWL: 133850984 |
| [NesterovSolve] Iter: 370 overflow: 0.412581 HPWL: 133647377 |
| [NesterovSolve] Iter: 380 overflow: 0.410272 HPWL: 133436776 |
| [NesterovSolve] Iter: 390 overflow: 0.407735 HPWL: 133225309 |
| [NesterovSolve] Iter: 400 overflow: 0.407744 HPWL: 133019319 |
| [NesterovSolve] Iter: 410 overflow: 0.407641 HPWL: 132822322 |
| [NesterovSolve] Iter: 420 overflow: 0.409961 HPWL: 132631346 |
| [NesterovSolve] Iter: 430 overflow: 0.412614 HPWL: 132431468 |
| [NesterovSolve] Iter: 440 overflow: 0.415571 HPWL: 132215291 |
| [NesterovSolve] Iter: 450 overflow: 0.417887 HPWL: 131976400 |
| [NesterovSolve] Iter: 460 overflow: 0.416801 HPWL: 131709061 |
| [NesterovSolve] Iter: 470 overflow: 0.408445 HPWL: 131393650 |
| [NesterovSolve] Iter: 480 overflow: 0.402646 HPWL: 131013018 |
| [NesterovSolve] Iter: 490 overflow: 0.38069 HPWL: 130605240 |
| [NesterovSolve] Iter: 500 overflow: 0.38069 HPWL: 130279763 |
| [NesterovSolve] Iter: 510 overflow: 0.38069 HPWL: 130078763 |
| [NesterovSolve] Iter: 520 overflow: 0.395401 HPWL: 129590925 |
| [NesterovSolve] Iter: 530 overflow: 0.360082 HPWL: 129052370 |
| [NesterovSolve] Iter: 540 overflow: 0.318836 HPWL: 129138976 |
| [NesterovSolve] Iter: 550 overflow: 0.257961 HPWL: 129017130 |
| [INFO GPL-0100] worst slack 4.96e-08 |
| [INFO GPL-0103] Weighted 26 nets. |
| [INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0 |
| [INFO GPL-0036] TileLxLy: 0 0 |
| [INFO GPL-0037] TileSize: 16800 16800 |
| [INFO GPL-0038] TileCnt: 178 178 |
| [INFO GPL-0039] numRoutingLayers: 5 |
| [INFO GPL-0040] NumTiles: 31684 |
| [INFO GPL-0063] TotalRouteOverflowH2: 0.0 |
| [INFO GPL-0064] TotalRouteOverflowV2: 0.0 |
| [INFO GPL-0065] OverflowTileCnt2: 0 |
| [INFO GPL-0066] 0.5%RC: 0.9663330179870508 |
| [INFO GPL-0067] 1.0%RC: 0.8828890398738867 |
| [INFO GPL-0068] 2.0%RC: 0.7077922112348547 |
| [INFO GPL-0069] 5.0%RC: 0.5418813589982928 |
| [INFO GPL-0070] 0.5rcK: 1.0 |
| [INFO GPL-0071] 1.0rcK: 1.0 |
| [INFO GPL-0072] 2.0rcK: 0.0 |
| [INFO GPL-0073] 5.0rcK: 0.0 |
| [INFO GPL-0074] FinalRC: 0.92461103 |
| [NesterovSolve] Iter: 560 overflow: 0.197035 HPWL: 128680790 |
| [NesterovSolve] Iter: 570 overflow: 0.288183 HPWL: 128830905 |
| [NesterovSolve] Iter: 580 overflow: 0.176777 HPWL: 128454547 |
| [NesterovSolve] Iter: 590 overflow: 0.166713 HPWL: 128119680 |
| [NesterovSolve] Iter: 600 overflow: 0.157896 HPWL: 127977288 |
| [INFO GPL-0100] worst slack 4.96e-08 |
| [INFO GPL-0103] Weighted 26 nets. |
| [NesterovSolve] Iter: 610 overflow: 0.131886 HPWL: 127865664 |
| [NesterovSolve] Iter: 620 overflow: 0.126018 HPWL: 127799881 |
| [NesterovSolve] Iter: 630 overflow: 0.127877 HPWL: 127812869 |
| [NesterovSolve] Iter: 640 overflow: 0.112207 HPWL: 127775897 |
| [NesterovSolve] Finished with Overflow: 0.095834 |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/7-global.odb... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/7-global.def... |
| [INFO]: Setting RC values... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.95 1.13 1.13 v _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[10] (net) |
| 0.95 0.04 1.17 v _096_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.29 0.32 1.49 ^ _096_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _046_ (net) |
| 0.29 0.00 1.49 ^ _099_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.72 v _099_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _014_ (net) |
| 0.29 0.00 1.72 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.72 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.72 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.43 slack (MET) |
| |
| |
| Startpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _122_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.96 1.13 1.13 v _122_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[6] (net) |
| 0.96 0.04 1.17 v _086_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.29 0.32 1.49 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _040_ (net) |
| 0.29 0.00 1.49 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.72 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _010_ (net) |
| 0.29 0.00 1.73 v _122_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.73 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _122_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.73 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.44 slack (MET) |
| |
| |
| Startpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _118_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.97 1.14 1.14 v _118_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[2] (net) |
| 0.98 0.04 1.18 v _076_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.29 0.32 1.50 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _034_ (net) |
| 0.29 0.00 1.50 ^ _079_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 1.73 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _006_ (net) |
| 0.29 0.00 1.74 v _118_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.74 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _118_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.74 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.45 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.96 1.14 1.14 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[14] (net) |
| 0.97 0.04 1.18 v _106_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.30 0.33 1.50 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _052_ (net) |
| 0.30 0.00 1.50 ^ _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.74 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _018_ (net) |
| 0.30 0.00 1.75 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.75 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.75 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.46 slack (MET) |
| |
| |
| Startpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _114_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.98 1.14 1.14 v _114_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[18] (net) |
| 0.99 0.04 1.19 v _064_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.29 0.33 1.51 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _026_ (net) |
| 0.29 0.00 1.51 ^ _068_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.30 0.24 1.75 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _002_ (net) |
| 0.30 0.00 1.75 v _114_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.75 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _114_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.04 0.29 library hold time |
| 0.29 data required time |
| ----------------------------------------------------------------------------- |
| 0.29 data required time |
| -1.75 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.46 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.51 0.30 13.30 ^ wb_rst_i (in) |
| 2 0.03 wb_rst_i (net) |
| 0.51 0.00 13.30 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.34 0.40 13.69 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _021_ (net) |
| 0.34 0.00 13.69 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.30 0.27 13.96 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.30 0.00 13.96 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.23 0.41 14.37 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _023_ (net) |
| 0.23 0.00 14.37 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.62 0.44 14.81 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _004_ (net) |
| 0.62 0.00 14.82 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.82 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.68 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _120_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.51 0.30 13.30 ^ wb_rst_i (in) |
| 2 0.03 wb_rst_i (net) |
| 0.51 0.00 13.30 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.34 0.40 13.69 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _021_ (net) |
| 0.34 0.00 13.69 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.30 0.27 13.96 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.30 0.00 13.96 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.23 0.41 14.37 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _023_ (net) |
| 0.23 0.00 14.37 v _083_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.62 0.44 14.81 ^ _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _008_ (net) |
| 0.62 0.00 14.82 ^ _120_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.82 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _120_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.68 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.51 0.30 13.30 ^ wb_rst_i (in) |
| 2 0.03 wb_rst_i (net) |
| 0.51 0.00 13.30 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.34 0.40 13.69 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _021_ (net) |
| 0.34 0.00 13.69 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.30 0.27 13.96 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.30 0.00 13.96 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.24 0.42 14.37 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _030_ (net) |
| 0.24 0.00 14.37 v _103_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.61 0.44 14.81 ^ _103_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _016_ (net) |
| 0.61 0.00 14.82 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.82 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.68 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _124_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.51 0.30 13.30 ^ wb_rst_i (in) |
| 2 0.03 wb_rst_i (net) |
| 0.51 0.00 13.30 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.34 0.40 13.69 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _021_ (net) |
| 0.34 0.00 13.69 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.30 0.27 13.96 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.30 0.00 13.96 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.23 0.41 14.37 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _023_ (net) |
| 0.23 0.00 14.37 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.61 0.44 14.81 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _012_ (net) |
| 0.61 0.00 14.81 ^ _124_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.81 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _124_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.81 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.69 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _119_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.51 0.30 13.30 ^ wb_rst_i (in) |
| 2 0.03 wb_rst_i (net) |
| 0.51 0.00 13.30 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.34 0.40 13.69 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _021_ (net) |
| 0.34 0.00 13.69 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.30 0.27 13.96 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.30 0.00 13.96 v _069_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.24 0.42 14.37 v _069_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _030_ (net) |
| 0.24 0.00 14.38 v _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.62 0.43 14.80 ^ _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _007_ (net) |
| 0.62 0.00 14.81 ^ _119_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.81 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _119_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.81 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.69 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _116_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.51 0.30 13.30 ^ wb_rst_i (in) |
| 2 0.03 wb_rst_i (net) |
| 0.51 0.00 13.30 ^ _057_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.34 0.40 13.69 ^ _057_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _021_ (net) |
| 0.34 0.00 13.69 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.30 0.27 13.96 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _022_ (net) |
| 0.30 0.00 13.96 v _059_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.23 0.41 14.37 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _023_ (net) |
| 0.23 0.00 14.37 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.62 0.44 14.81 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.02 _004_ (net) |
| 0.62 0.00 14.82 ^ _116_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 14.82 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _116_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 64.50 library setup time |
| 64.50 data required time |
| ----------------------------------------------------------------------------- |
| 64.50 data required time |
| -14.82 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.68 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 49.68 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 1.43 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _112_/CLK ^ |
| 0.16 |
| _112_/CLK ^ |
| 0.15 0.00 0.02 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 1.67e-04 3.57e-05 4.08e-09 2.03e-04 86.9% |
| Combinational 1.50e-05 1.48e-05 7.40e-07 3.05e-05 13.1% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 1.82e-04 5.04e-05 7.44e-07 2.33e-04 100.0% |
| 78.1% 21.6% 0.3% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 66668 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/7-global.odb... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_04_16_09/tmp/placement/7-global.def... |
