openlane/user_project_wrapper/config.json

{
    "DESIGN_NAME": "user_project_wrapper",
    "DESIGN_IS_CORE": 1,
    "RT_MAX_LAYER": "Metal4",
    "GRT_ALLOW_CONGESTION":0,
    "SYNTH_EXTRA_MAPPING_FILE":"$script_dir/latch_map.v",
    "VERILOG_FILES": [
    "dir::../../verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/sky130_sram_1kbyte_1rw1r_32x256_8.v",
    "dir::../../verilog/rtl_sram_out_cache/caravel/defines.v",
    "dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v",
	"dir::../../verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v",
    "dir::../../verilog/rtl_sram_out_cache/bus_arbiter.v",
    "dir::../../verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffe.v",
    "dir::../../verilog/rtl_sram_out_cache/hehe/src/cache/cacheblock/std_dffr.v",
    "dir::../../verilog/rtl_sram_out_cache/hehe/src/cache/l1dcache.v",
    "dir::../../verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v",
    "dir::../../verilog/rtl_sram_out_cache/caravel_defines.v",
    "dir::../../verilog/rtl_sram_out_cache/inc/rvj1_defines.v",
	"dir::../../verilog/rtl_sram_out_cache/rvj1_caravel_soc.v",
	"dir::../../verilog/rtl_sram_out_cache/instr_ram_mux.v",
	"dir::../../verilog/rtl_sram_out_cache/data_ram_mux.v",
	"dir::../../verilog/rtl_sram_out_cache/wishbone_mux.v",
	"dir::../../verilog/rtl_sram_out_cache/gpio.v",
	"dir::../../verilog/rtl_sram_out_cache/timer.v",
    "dir::../../verilog/rtl_sram_out_cache/top.v",
    "dir::../../verilog/rtl_sram_out_cache/user_project_wrapper.v"
    ],
    "CLOCK_PERIOD": 20,
    "CLOCK_PORT": "user_clock2",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY": 0.4,
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 0,
    "FP_PDN_VPITCH": 180,
    "FP_PDN_HPITCH": 180,
    "CLOCK_TREE_SYNTH": 0,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "MAGIC_ZEROIZE_ORIGIN": 0,
    "FP_SIZING": "absolute",
    "UNIT": "2.4",
    "FP_IO_VEXTEND": "expr::2 * $UNIT",
    "FP_IO_HEXTEND": "expr::2 * $UNIT",
    "FP_IO_VLENGTH": "ref::$UNIT",
    "FP_IO_HLENGTH": "ref::$UNIT",
    "FP_IO_VTHICKNESS_MULT": 4,
    "FP_IO_HTHICKNESS_MULT": 4,
    "FP_PDN_CORE_RING": 1,
    "FP_PDN_CORE_RING_VWIDTH": 3.1,
    "FP_PDN_CORE_RING_HWIDTH": 3.1,
    "FP_PDN_CORE_RING_VOFFSET": 12.45,
    "FP_PDN_CORE_RING_HOFFSET": 12.45,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "FP_PDN_VWIDTH": 3.1,
    "FP_PDN_HWIDTH": 3.1,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "ROUTING_CORES": 48,
    "LVS_CONNECT_BY_LABEL": 1,
    "RUN_KLAYOUT_XOR":0,
    "KLAYOUT_XOR_GDS":0,
    "KLAYOUT_XOR_XML":0,
    "RUN_KLAYOUT":0,
    "RUN_MAGIC_DRC":0,
    "RUN_KLAYOUT_DRC":0,
    "QUIT_ON_LVS_ERROR":0,
    "QUIT_ON_MAGIC_DRC":0,
    "QUIT_ON_NEGATIVE_WNS":0,
    "QUIT_ON_SLEW_VIOLATIONS":0,
    "QUIT_ON_TIMING_VIOLATIONS":0,
    "VDD_PIN":"vdd",
    "GND_PIN":"vss",
     "pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "RT_MAX_LAYER": "met4",
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hdll": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 8
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 10,
            "SYNTH_MAX_FANOUT": 5
        },
        "scl::sky130_fd_sc_ms": {
            "CLOCK_PERIOD": 10
        }
    },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "FP_PDN_CHECK_NODES": 0,
        "FP_PDN_ENABLE_RAILS": 0,
        "RT_MAX_LAYER": "Metal4",
        "DIE_AREA": "0 0 3000 3000",
        "PL_TARGET_DENSITY": 0.36,
        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
        "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
        "DIODE_INSERTION_STRATEGY": 4,
        "FP_PDN_CHECK_NODES": 0,
        "MAGIC_WRITE_FULL_LEF": 0,
        "FP_PDN_ENABLE_RAILS": 0
   }
}