update
diff --git a/README.md b/README.md index b155839..c9fd837 100644 --- a/README.md +++ b/README.md
@@ -1,3 +1,20 @@ +<!--- +# SPDX-FileCopyrightText: 2020 RIOS Lab +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 +--> + # RIOS Lab GreenRio1.0 RISC-V Processor GF180 Version [](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
diff --git a/verilog/base.sdc b/verilog/base.sdc index 0b64f49..10e4ed4 100755 --- a/verilog/base.sdc +++ b/verilog/base.sdc
@@ -1,3 +1,19 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http:#www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Include caravel global defines for the number of the user project IO pads ############################################################################### # Created by write_sdc # Wed Nov 10 17:01:46 2021
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v index 44a29a0..0a7b96c 100644 --- a/verilog/rtl/defines.v +++ b/verilog/rtl/defines.v
@@ -50,6 +50,22 @@ // not really parameterized but just to easily keep track of the number // of ram_block across different modules +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +// Include caravel global defines for the number of the user project IO pads `define RAM_BLOCKS 1 // Clock divisor default value
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v index 5f1ba27..0954f62 100644 --- a/verilog/rtl/user_defines.v +++ b/verilog/rtl/user_defines.v
@@ -25,20 +25,18 @@ // Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v // Useful GPIO mode values. These match the names used in defs.h. // -`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 13'h0403 -`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 13'h0c01 -`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 13'h0801 -`define GPIO_MODE_MGMT_STD_OUTPUT 13'h1809 -`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 13'h1801 -`define GPIO_MODE_MGMT_STD_ANALOG 13'h000b -`define GPIO_MODE_USER_STD_INPUT_NOPULL 13'h0402 -`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 13'h0c00 -`define GPIO_MODE_USER_STD_INPUT_PULLUP 13'h0800 -`define GPIO_MODE_USER_STD_OUTPUT 13'h1808 -`define GPIO_MODE_USER_STD_BIDIRECTIONAL 13'h1800 -`define GPIO_MODE_USER_STD_OUT_MONITORED 13'h1802 -`define GPIO_MODE_USER_STD_ANALOG 13'h000a +`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 10'h007 +`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 10'h047 +`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 10'h087 +`define GPIO_MODE_MGMT_STD_OUTPUT 10'h00b +`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 10'h009 + +`define GPIO_MODE_USER_STD_INPUT_NOPULL 10'h006 +`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 10'h046 +`define GPIO_MODE_USER_STD_INPUT_PULLUP 10'h086 +`define GPIO_MODE_USER_STD_OUTPUT 10'h00a +`define GPIO_MODE_USER_STD_BIDIRECTIONAL 10'h008 // The power-on configuration for GPIO 0 to 4 is fixed and cannot be // modified (allowing the SPI and debug to always be accessible unless @@ -52,41 +50,41 @@ // up in a state that can be used immediately without depending on // the management SoC to run a startup program to configure the GPIOs. -`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_MGMT_STD_INPUT_PULLDOWN -`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_MGMT_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_MGMT_STD_OUTPUT -`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_MGMT_STD_BIDIRECTIONAL -`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_MGMT_STD_ANALOG -`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN -`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP +`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_INVALID // Configurations of GPIO 14 to 24 are used on caravel but not caravan. -`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL -`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_OUT_MONITORED -`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_ANALOG -`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_MGMT_STD_INPUT_PULLDOWN -`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_MGMT_STD_BIDIRECTIONAL -`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_MGMT_STD_ANALOG -`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN -`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP +`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP -`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP +`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_INVALID `endif // __USER_DEFINES_H \ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 26081e9..f7f2360 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -39,8 +39,8 @@ parameter BITS = 32 )( `ifdef USE_POWER_PINS - inout vccd1, // User area 1 1.8V supply - inout vssd1, // User area 1 digital ground + inout vdd, // User area 1 1.8V supply + inout vss, // User area 1 digital ground `endif // Wishbone Slave ports (WB MI A) @@ -56,9 +56,9 @@ output [31:0] wbs_dat_o, // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, + input [63:0] la_data_in, + output [63:0] la_data_out, + input [63:0] la_oenb, // IOs input [`MPRJ_IO_PADS-1:0] io_in, @@ -162,4 +162,4 @@ end endmodule -`default_nettype wire +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl_sram_out_cache/hehe/src/base.sdc b/verilog/rtl_sram_out_cache/hehe/src/base.sdc index 837fb81..e3f6119 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/base.sdc +++ b/verilog/rtl_sram_out_cache/hehe/src/base.sdc
@@ -1,3 +1,18 @@ +# SPDX-FileCopyrightText: 2022 RIOSLab +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http:#www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 ############################################################################### # Created by write_sdc # Wed Nov 10 17:01:46 2021
diff --git a/verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v b/verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v index 1774b55..2e54145 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v +++ b/verilog/rtl_sram_out_cache/hehe/src/cache/l1icache_32.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module l1icache_32 #( parameter VIRTUAL_ADDR_LEN = 32,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/cache/params.vh b/verilog/rtl_sram_out_cache/hehe/src/cache/params.vh index b8deb41..99cb6d2 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/cache/params.vh +++ b/verilog/rtl_sram_out_cache/hehe/src/cache/params.vh
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef PARAMS_VH `define PARAMS_VH // MACROS
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v index d30e30c..9d16bff 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/core_empty.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `include "params.vh" module core_empty #( parameter XLEN = 64,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v index b8ed12e..b2b1eed 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/ac.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 ///////////////////////// // Author: Peichen Guo // // RIOS Lab work //
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v index 1b7c0ed..70ceb3b 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/agu.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 ///////////////////////// // Author: Peichen Guo // // RIOS Lab work //
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v index 7a80177..bafa4a2 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/cu.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 ///////////////////////// // Author: Peichen Guo // // RIOS Lab work //
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v index 567cdf2..c4411bc 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lr.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 ///////////////////////// // Author: Peichen Guo // // RIOS Lab work //
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v index 5d069fe..56a276c 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/lsq.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 ///////////////////////// // Author: Peichen Guo // // RIOS Lab work //
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v index 635f952..9b9c39a 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/nblsu.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 ///////////////////////// // Author: Peichen Guo // // RIOS Lab work //
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/params.vh b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/params.vh index b8deb41..99cb6d2 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/params.vh +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/lsu/params.vh
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef PARAMS_VH `define PARAMS_VH // MACROS
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/leaf_pte_check.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/leaf_pte_check.v deleted file mode 100755 index 8225b3e..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/leaf_pte_check.v +++ /dev/null
@@ -1,83 +0,0 @@ -`include "../params.vh" -module leaf_pte_check - #( - parameter PTE_SIZE_IN_BIT = 64 -) - ( - - input [1:0] access_mode_i, - input csr_sstatus_mxr_i, - input csr_sstatus_sum_i, - input [1:0] priviledge_level_i, - input [1:0] page_table_level_i, - - input pte_active_i, - input [PTE_SIZE_IN_BIT - 1 : 0] pte_i, - input pte_is_leaf_i, - - output pte_valid_o, - output page_fault_valid_o -); - reg page_fault_valid; - - - initial begin - page_fault_valid = 0; - end - - - always @(*) begin - if (pte_active_i && pte_is_leaf_i) begin - // Step 5: Check access mode - if ((access_mode_i == ACCESS_MODE_READ) - && (!pte_i[`pte_r] && !(pte_i[`pte_x] && csr_sstatus_mxr_i)))begin - page_fault_valid = 1; - $display("cause : 1"); - end - else if ((access_mode_i == ACCESS_MODE_WRITE) - && (!pte_i[`pte_w]))begin - page_fault_valid = 1; - $display("cause : 2"); - end - else if ((access_mode_i == ACCESS_MODE_EXECUTE) - && (!pte_i[`pte_x]))begin - page_fault_valid = 1; - $display("cause : 3"); - end - - - // Step 5: Check priviledge level - else if ((priviledge_level_i == U_MODE) && !pte_i[`pte_u])begin - page_fault_valid = 1; - $display("cause : 4"); - end - else if ((priviledge_level_i == S_MODE) && pte_i[`pte_u] && !csr_sstatus_sum_i)begin - page_fault_valid = 1; - $display("cause : 5"); - end - - // Step 6: misaligned superpage check - else if (((pte_i[`pte_ppn0] != 0) && (page_table_level_i > 0)) || - ((pte_i[`pte_ppn1]!= 0) && (page_table_level_i > 1)))begin - page_fault_valid = 1; - $display("cause : 6"); - end - - - // Step 7: - else if (!pte_i[`pte_a] || ((access_mode_i == ACCESS_MODE_WRITE) && !pte_i[`pte_d]))begin - page_fault_valid = 1; - $display("cause : 7"); - end - else - page_fault_valid = 0; - - end else begin - page_fault_valid = 0; - end - end - - assign pte_valid_o = ~page_fault_valid; - assign page_fault_valid_o = page_fault_valid; - -endmodule : leaf_pte_check
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/mmu_sv39.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/mmu_sv39.v deleted file mode 100755 index 10b2dd4..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/mmu_sv39.v +++ /dev/null
@@ -1,342 +0,0 @@ - -`include "../params.vh" -module mmu_sv39 - #( - parameter PTE_SIZE = 8, - parameter PTE_SIZE_IN_BIT = 64, - parameter PAGE_TABLE_LEVELS = 3, - - parameter VIRTUAL_ADDR_LEN_SV39 = 39, - parameter PHYSICAL_ADDR_LEN_SV39 = 56, - parameter PAGE_OFFSET_WIDTH = 12, - - parameter VPN_WIDTH = 27, - parameter VPN_SLICE_WIDTH = 9, - parameter PPN_WIDTH = 44, - parameter PPN_SLICE_0_WIDTH = 9, - parameter PPN_SLICE_1_WIDTH = 9, - parameter PPN_SLICE_2_WIDTH = 26 -) - ( - input clk, - input rstn, - - input flush_i, - - input [63:0] csr_satp_i, - input [63:0] csr_mstatus_i, - input [1:0] priviledge_level_i, - - input [1:0] access_mode_i, - - // AGU -> MMU - input lsu_req_valid_i, - input [VIRTUAL_ADDR_LEN_SV39 - 1 : 0] lsu_req_addr_i, - output lsu_req_ready_o, - // MMU -> AGU - output lsu_resp_valid_o, - output [PHYSICAL_ADDR_LEN_SV39 - 1 : 0] lsu_resp_addr_o, - input lsu_resp_ready_i, - - // MMU -> Cache - output ptw_req_valid_o, - output [PHYSICAL_ADDR_LEN_SV39 - 1 : 0] ptw_req_addr_o, - output [5:0] ptw_req_len_o, - input ptw_req_ready_i, - // Cache -> MMU - input ptw_resp_valid_i, - input [PTE_SIZE_IN_BIT - 1 : 0] ptw_resp_pte_i, - output ptw_resp_ready_o, - - // Fault - output page_fault_valid_o, - output [3:0] page_fault_cause_o -); - initial begin - $dumpfile("wave.vcd"); - $dumpvars; - $dumpon; - $dumpall; - $dumpflush; - end - - // M0 Stage - // get input data from LSU/FETCH/CACHE - - // Control signal - // LSU - wire m0_lsu_clk_en, m0_lsu_ready, m0_lsu_valid; - // CACHE - wire m0_ptw_clk_en, m0_ptw_ready, m0_ptw_valid; - // Payload - // LSU - reg m0_lsu_valid_d, m0_lsu_valid_q; - reg [1:0] m0_priviledge_level_d, m0_priviledge_level_q; - reg m0_mprv_d, m0_mprv_q; - reg [1:0] m0_mpp_d, m0_mpp_q; - reg m0_smxr_d, m0_smxr_q; - reg m0_ssum_d, m0_ssum_q; - reg [SATP_PPN_WIDTH - 1 : 0] m0_satp_ppn_d, m0_satp_ppn_q; - reg [SATP_ASID_WIDTH - 1 : 0] m0_satp_asid_d, m0_satp_asid_q; - reg [SATP_MODE_WIDTH - 1 : 0] m0_satp_mode_d, m0_satp_mode_q; - reg [VIRTUAL_ADDR_LEN_SV39 - 1 : 0] m0_virtual_address_d, m0_virtual_address_q; - reg [1:0] m0_access_mode_d, m0_access_mode_q; - reg [1:0] m0_init_page_table_level_d, m0_init_page_table_level_q; - // CACHE - reg m0_ptw_valid_d, m0_ptw_valid_q; - reg [PTE_SIZE_IN_BIT - 1 : 0] m0_ptw_pte_d, m0_ptw_pte_q; - reg [1:0] m0_ptw_page_table_level_d, m0_ptw_page_table_level_q; - - - // M1 Stage - // Process and generate output - - // Control signal - wire m1_lsu_clk_en, m1_lsu_valid, m1_lsu_ready; - wire m1_ptw_clk_en, m1_ptw_valid, m1_ptw_ready; - - wire m1_stall_m0_lsu, m1_stall_m0_ptw; - wire m1_serve_ptw, m1_serve_lsu; - - // Payload - reg m1_lsu_valid_d, m1_lsu_valid_q; - reg m1_ptw_valid_d, m1_ptw_valid_q; - reg [PHYSICAL_ADDR_LEN_SV39 - 1 : 0] m1_lsu_resp_addr_d, m1_lsu_resp_addr_q; - reg [PHYSICAL_ADDR_LEN_SV39 - 1 : 0] m1_ptw_req_addr_d, m1_ptw_req_addr_q; - reg m1_page_fault_valid_d, m1_page_fault_valid_q; - reg [3:0] m1_page_fault_cause_d, m1_page_fault_cause_q; - - // Intermediate register - reg [1:0] m1_page_table_level; - reg [PPN_SLICE_2_WIDTH -1 : 0] m1_ppn2; - reg [PPN_SLICE_1_WIDTH -1 : 0] m1_ppn1; - reg [PPN_SLICE_0_WIDTH -1 : 0] m1_ppn0; - reg [PAGE_OFFSET_WIDTH -1 : 0] m1_pgoff; - - wire m1_req_next_level_pte; - wire m1_pte_is_leaf; - wire m1_pte_valid_leaf; - - wire m1_page_fault_valid_illegal_page_table_level; - wire m1_page_fault_valid_illegal_req; - wire m1_page_fault_valid_invalid_pte; - wire m1_page_fault_valid_inaccessable_leaf_pte; - - - // Status management - reg m0_lsu_active_d, m0_lsu_active_q; - reg m0_ptw_active_d, m0_ptw_active_q; - - assign m0_lsu_active_d = m0_ptw_valid ? 1'b0 : (m0_lsu_valid ? 1'b1 : m0_lsu_active_q); - assign m0_ptw_active_d = (m1_pte_is_leaf | m1_page_fault_valid_d) ? 1'b0: (m0_ptw_valid ? 1'b1 : m0_ptw_active_q); - - - - // M0 Stage - // Output - assign lsu_req_ready_o = m0_lsu_ready & m0_ptw_ready; - assign ptw_resp_ready_o = m0_ptw_ready; - - // LSU - // Control - assign m0_lsu_clk_en = m0_lsu_ready & m0_lsu_valid; - assign m0_lsu_ready = ~m1_stall_m0_lsu; - assign m0_lsu_valid = m0_lsu_ready & lsu_req_valid_i; - // Payload - assign m0_lsu_valid_d = ~flush_i & (m1_stall_m0_lsu ? m0_lsu_valid_q : m0_lsu_clk_en); - assign m0_priviledge_level_d = priviledge_level_i; - assign m0_mprv_d = csr_mstatus_i[17]; - assign m0_mpp_d = csr_mstatus_i[12:11]; - assign m0_smxr_d = csr_mstatus_i[`sstatus_mxr]; - assign m0_ssum_d = csr_mstatus_i[`sstatus_sum]; - assign m0_satp_ppn_d = csr_satp_i[SATP_PPN_WIDTH - 1 : 0]; - assign m0_satp_asid_d = csr_satp_i[SATP_ASID_WIDTH + SATP_PPN_WIDTH - 1 : SATP_PPN_WIDTH]; - assign m0_satp_mode_d = csr_satp_i[XLEN - 1 : XLEN - SATP_MODE_WIDTH]; - assign m0_virtual_address_d = lsu_req_addr_i; - assign m0_access_mode_d = access_mode_i; - assign m0_init_page_table_level_d = PAGE_TABLE_LEVELS - 1; - // CACHE - // Control - assign m0_ptw_clk_en = m0_ptw_ready & m0_ptw_valid; - assign m0_ptw_ready = ~m1_stall_m0_ptw; - assign m0_ptw_valid = m0_ptw_ready & ptw_resp_valid_i; - // Payload - assign m0_ptw_valid_d = ~flush_i & (m1_stall_m0_ptw ? m0_ptw_valid_q : m0_ptw_clk_en); - assign m0_ptw_pte_d = ptw_resp_pte_i; - - assign m0_ptw_page_table_level_d = m1_serve_ptw ? ((m0_ptw_page_table_level_q == 0) ? 0 : m0_ptw_page_table_level_q - 1) : m0_init_page_table_level_q; - - - // M1 Stage - - // Output - assign lsu_resp_valid_o = m1_lsu_valid_q & ~m1_page_fault_valid_q; - assign lsu_resp_addr_o = m1_lsu_resp_addr_q; - - assign ptw_req_valid_o = m1_ptw_valid_q & ~m1_page_fault_valid_q; - assign ptw_req_addr_o = m1_ptw_req_addr_q; - assign ptw_req_len_o = PTE_SIZE; - - assign page_fault_valid_o = m1_page_fault_valid_q; - assign page_fault_cause_o = m1_page_fault_cause_q; - - - // Internal logic - - - // If ptw is activated, lsu requeset should be blocked - // Priority: ptw > lsu - assign m1_stall_m0_lsu = m0_lsu_valid_q & (~m1_ptw_ready | ~m1_lsu_ready | m1_serve_ptw); - assign m1_stall_m0_ptw = m1_serve_ptw & (~m1_ptw_ready | ~m1_lsu_ready); - - assign m1_lsu_clk_en = m1_lsu_valid & m1_lsu_ready; - // @FIXME - assign m1_lsu_valid = m1_lsu_ready & ((m0_ptw_valid_q & m1_pte_is_leaf) | m1_page_fault_valid_d); - assign m1_lsu_ready = lsu_resp_ready_i; - - assign m1_ptw_clk_en = m1_ptw_valid & m1_ptw_ready; - // @FIXME - assign m1_ptw_valid = ptw_req_ready_i & ((m0_lsu_valid_q | m0_ptw_valid_q) & m1_req_next_level_pte | m1_page_fault_valid_d); - assign m1_ptw_ready = ptw_req_ready_i; - - assign m1_lsu_valid_d = ~flush_i & m1_lsu_valid; - assign m1_ptw_valid_d = ~flush_i & m1_ptw_valid; - - - assign m1_serve_ptw = m0_ptw_active_q; - assign m1_serve_lsu = m0_lsu_active_q; - assign m1_page_table_level = m1_serve_lsu ? m0_init_page_table_level_q : m0_ptw_page_table_level_q; - - // Page fault logic - assign m1_page_fault_valid_illegal_req = m1_serve_lsu & (m0_satp_ppn_q == 0); - assign m1_page_fault_valid_illegal_page_table_level = (m1_page_table_level == 0) & m1_req_next_level_pte; - - assign m1_page_fault_valid_d = m1_page_fault_valid_inaccessable_leaf_pte | m1_page_fault_valid_invalid_pte | m1_page_fault_valid_illegal_req | m1_page_fault_valid_illegal_page_table_level; - assign m1_page_fault_cause_d = (m0_access_mode_q == ACCESS_MODE_READ) ? EXCEPTION_LOAD_PAGE_FAULT : ((m0_access_mode_q == ACCESS_MODE_WRITE) ? EXCEPTION_STORE_PAGE_FAULT : EXCEPTION_INSTR_PAGE_FAULT); - - // Generate lsu response physical address - assign m1_ppn2 = ((m1_page_table_level <= 2) && m1_serve_ptw) ? m0_ptw_pte_q[`pte_ppn2] : {17'b0, m0_virtual_address_q[`va_vpn2]}; - assign m1_ppn1 = ((m1_page_table_level <= 1) && m1_serve_ptw) ? m0_ptw_pte_q[`pte_ppn1] : m0_virtual_address_q[`va_vpn1]; - assign m1_ppn0 = ((m1_page_table_level <= 0) && m1_serve_ptw) ? m0_ptw_pte_q[`pte_ppn0] : m0_virtual_address_q[`va_vpn0]; - assign m1_pgoff = m0_virtual_address_q[PAGE_OFFSET_WIDTH - 1 :0]; - assign m1_lsu_resp_addr_d = {m1_ppn2, m1_ppn1, m1_ppn0, m1_pgoff}; - - // Generate ptw requeset ppn - ptw #( - .PTE_SIZE (PTE_SIZE), - .PTE_SIZE_IN_BIT (PTE_SIZE_IN_BIT), - .VIRTUAL_ADDR_LEN_SV39 (VIRTUAL_ADDR_LEN_SV39), - .PHYSICAL_ADDR_LEN_SV39 (PHYSICAL_ADDR_LEN_SV39), - .PAGE_OFFSET_WIDTH (PAGE_OFFSET_WIDTH), - .VPN_SLICE_WIDTH (VPN_SLICE_WIDTH) - ) ptw ( - .ptw_enable_i (m1_serve_ptw | m1_serve_lsu), - .page_table_level_i (m1_page_table_level), - .virtual_address_i (m0_virtual_address_q), - .pte_active_i (m1_serve_ptw), - .pte_i (m0_ptw_pte_q), - .satp_ppn_i (m0_satp_ppn_q), - .pte_is_leaf_o (m1_pte_is_leaf), - .req_next_level_pte_o (m1_req_next_level_pte), - .pte_req_address_o (m1_ptw_req_addr_d), - .page_fault_valid_o (m1_page_fault_valid_invalid_pte) - - ); - - leaf_pte_check #( - .PTE_SIZE_IN_BIT(PTE_SIZE_IN_BIT) - ) ptw_leaf ( - .access_mode_i (m0_access_mode_q), - .csr_sstatus_mxr_i (m0_smxr_q), - .csr_sstatus_sum_i (m0_ssum_q), - .priviledge_level_i (m0_priviledge_level_q), - .page_table_level_i (m1_page_table_level), - .pte_active_i (m1_serve_ptw), - .pte_i (m0_ptw_pte_q), - .pte_is_leaf_i (m1_pte_is_leaf), - .pte_valid_o (m1_pte_valid_leaf), - .page_fault_valid_o (m1_page_fault_valid_inaccessable_leaf_pte) - ); - - - always @(posedge clk) begin : m0_lsu_valid_dff - if (~rstn) begin - m0_lsu_valid_q <= 1'b0; - m0_lsu_active_q <= 1'b0; - end else begin - m0_lsu_valid_q <= m0_lsu_valid_d; - m0_lsu_active_q <= m0_lsu_active_d; - end - end - - always @(posedge clk) begin : m0_lsu_payload_dff - if (m0_lsu_clk_en) begin - m0_priviledge_level_q <= m0_priviledge_level_d; - m0_mprv_q <= m0_mprv_d; - m0_mpp_q <= m0_mpp_q; - m0_smxr_q <= m0_smxr_d; - m0_ssum_q <= m0_ssum_d; - m0_satp_ppn_q <= m0_satp_ppn_d; - m0_satp_asid_q <= m0_satp_asid_d; - m0_satp_mode_q <= m0_satp_mode_d; - m0_virtual_address_q <= m0_virtual_address_d; - m0_access_mode_q <= m0_access_mode_d; - m0_init_page_table_level_q <= m0_init_page_table_level_d; - end - end - - always @(posedge clk) begin : m0_ptw_valid_dff - if (~rstn) begin - m0_ptw_valid_q <= 1'b0; - m0_ptw_active_q <= 1'b0; - end else begin - m0_ptw_valid_q <= m0_ptw_valid_d; - m0_ptw_active_q <= m0_ptw_active_d; - end - end - - always @(posedge clk) begin : m0_ptw_payload_dff - if (m0_ptw_clk_en) begin - m0_ptw_pte_q <= m0_ptw_pte_d; - m0_ptw_page_table_level_q <= m0_ptw_page_table_level_d; - end - end - - always @(posedge clk) begin : m1_lsu_valid_dff - if (~rstn) begin - m1_lsu_valid_q <= 1'b0; - end else begin - m1_lsu_valid_q <= m1_lsu_valid_d; - end - end - - always @(posedge clk) begin : m1_lsu_payload_dff - if (m1_lsu_clk_en) begin - m1_lsu_resp_addr_q <= m1_lsu_resp_addr_d; - m1_page_fault_valid_q <= m1_page_fault_valid_d; - m1_page_fault_cause_q <= m1_page_fault_cause_d; - end - end - - always @(posedge clk) begin : m1_ptw_valid_dff - if (~rstn) begin - m1_ptw_valid_q <= 1'b0; - end else begin - m1_ptw_valid_q <= m1_ptw_valid_d; - end - end - - always @(posedge clk) begin : m1_ptw_payload_dff - if (m1_ptw_clk_en) begin - m1_ptw_req_addr_q <= m1_ptw_req_addr_d; - m1_page_fault_valid_q <= m1_page_fault_valid_d; - m1_page_fault_cause_q <= m1_page_fault_cause_d; - end - end - - // @TODO: TLB - -endmodule : mmu_sv39 - - -
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/ptw.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/ptw.v deleted file mode 100755 index d92b930..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/mmu/ptw.v +++ /dev/null
@@ -1,112 +0,0 @@ -`include "../params.vh" - -module ptw - # ( - parameter PTE_SIZE = 8, - parameter PTE_SIZE_IN_BIT = 64, - - parameter VIRTUAL_ADDR_LEN_SV39 = 39, - parameter PHYSICAL_ADDR_LEN_SV39 = 56, - parameter PAGE_OFFSET_WIDTH = 12, - - parameter VPN_SLICE_WIDTH = 9 -) - ( - input ptw_enable_i, - input [1:0] page_table_level_i, - - input [VIRTUAL_ADDR_LEN_SV39 - 1 : 0] virtual_address_i, - - input pte_active_i, - input [PTE_SIZE_IN_BIT - 1 : 0] pte_i, - input [SATP_PPN_WIDTH - 1 : 0] satp_ppn_i, - - - output pte_is_leaf_o, - output req_next_level_pte_o, - output [PHYSICAL_ADDR_LEN_SV39 - 1 : 0] pte_req_address_o, - - output page_fault_valid_o -); - reg pte_is_leaf; - reg req_next_level_pte; - reg [PHYSICAL_ADDR_LEN_SV39 - 1 : 0] pte_req_address; - reg [VPN_SLICE_WIDTH - 1: 0] pte_req_index; - - reg page_fault_valid; - - assign pte_is_leaf_o = pte_is_leaf; - assign req_next_level_pte_o = req_next_level_pte; - assign pte_req_address_o = pte_req_address; - assign page_fault_valid_o = page_fault_valid; - - - always @(*) begin - - if (ptw_enable_i) begin - - case (page_table_level_i) - 2'b10: pte_req_index = virtual_address_i[`va_vpn2]; - 2'b01: pte_req_index = virtual_address_i[`va_vpn1]; - 2'b00: pte_req_index = virtual_address_i[`va_vpn0]; - default: page_fault_valid = 1'b1; - endcase - - if (pte_active_i) begin - - pte_req_address = ({12'h000,pte_i[`pte_ppn]} << PAGE_OFFSET_WIDTH) + pte_req_index * PTE_SIZE; - - // Step 4: Leaf/Non-leaf pte check - casez ({pte_i[`pte_x],pte_i[`pte_w],pte_i[`pte_r],pte_i[`pte_v]}) - // pte.v = 0 ==> page fault - 4'b???0: begin - pte_is_leaf = 1'b0; - req_next_level_pte = 1'b0; - page_fault_valid = 1'b1; - end - // pte.r = 0 and pte.w = 1 ==> page fault - 4'b?101: begin - pte_is_leaf = 1'b0; - req_next_level_pte = 1'b0; - page_fault_valid = 1'b1; - end - // pte.x = 1 ==> leaf pte - // @TODO: x-only pte is for I-TLB - 4'b1001: begin - pte_is_leaf = 1'b1; - req_next_level_pte = 1'b0; - page_fault_valid = 1'b0; - end - // pte.r = 1 ==> leaf pte - 4'b??11: begin - pte_is_leaf = 1'b1; - req_next_level_pte = 1'b0; - page_fault_valid = 1'b0; - end - // default ==> request next level pte - default: begin - pte_is_leaf = 1'b0; - req_next_level_pte = 1'b1; - page_fault_valid = 1'b0; - end - endcase - - end else begin - pte_is_leaf = 1'b0; - req_next_level_pte = 1'b1; - pte_req_address = ({12'h000,satp_ppn_i} << PAGE_OFFSET_WIDTH) + pte_req_index * PTE_SIZE; - page_fault_valid = 1'b0; - end - - end else begin - pte_is_leaf = 1'b0; - req_next_level_pte = 1'b0; - pte_req_address = '0; - page_fault_valid = 1'b0; - end - - - end - -endmodule -
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh b/verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh index b8deb41..99cb6d2 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/params.vh
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef PARAMS_VH `define PARAMS_VH // MACROS
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v index e0249c7..e8a5b1d 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/backend.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 //gpc改一下backend哈，参照着core_empty改 `ifndef BACKEND_V `define BACKEND_V
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v index ea19fed..cbf3a0c 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/pipeline/frontend.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef FRONTEND_V `define FRONTEND_V
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v index 7a4aaae..f4a920c 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/btb.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module btb #( parameter BTB_SIZE = 4, parameter BTB_SIZE_1 = 3,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v index cfceb13..1452043 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module counter#( parameter CNT_SIZE = 32 + 8, parameter CNT_SIZE_WIDTH = 6
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v index 77b1ab7..04d2f99 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_rob.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module counter_rob#( parameter CNT_SIZE = 32 + 8, parameter CNT_SIZE_WIDTH = 6
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v index 2cd0a00..befa0a0 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/counter_tmp.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module counter_tmp#( parameter CNT_SIZE = 32 + 8, parameter CNT_SIZE_WIDTH = 6
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v index e4d5004..bb4eecd 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/csr.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef CSR_V `define CSR_V
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v index b01edc2..6b731e7 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/decode.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef DECODE_V `define DECODE_V
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v index 6665003..297f7d7 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/excep_ctrl.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `include "../params.vh" module excep_ctrl ( //from rob
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fake_icache.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fake_icache.v index 53335d4..ad0f777 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fake_icache.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fake_icache.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module fake_icache ( input clk, input reset,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v index d89ba49..d239f13 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fetch.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef FETCH_V `define FETCH_V // `include "../params.vh"
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v index 8c526f9..302af92 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module fifo #( //p0 is not in the fifo parameter FIFO_DATA_WIDTH = 5, parameter FIFO_SIZE = 32,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v index d1b93e5..2953664 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/fifo_tmp.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module fifo_tmp #( parameter FIFO_DATA_WIDTH = 5, parameter FIFO_SIZE = 32,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v index a17c0e1..379b1da 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/gshare.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module gshare #( parameter GSHARE_WIDTH = 4,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v index ce6fae8..072ed9c 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/ins_buffer.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module ins_buffer #( parameter INS_BUFFER_DATA = 96, parameter INS_BUFFER_SIZE = 8,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v index 782b080..01ad0c4 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_alu.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module new_alu( input clk, input rstn,
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v index a5173b4..9132a75 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/new_fu.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef FU_V `define FU_V
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v index 20cbb85..76f1095 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/physical_regfile.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module physical_regfile #( parameter REG_SIZE = 64, parameter REG_SIZE_WIDTH = 6
diff --git a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v index 7fb849e..85ff46f 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v +++ b/verilog/rtl_sram_out_cache/hehe/src/core_empty/units/rcu.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 // `include "/work/stu/yzhang/workspace/hehecore/src/params.vh" `include "../params.vh" module rcu (
diff --git a/verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds b/verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds deleted file mode 100755 index 7ed1528..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds +++ /dev/null Binary files differ
diff --git a/verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1rw1r_64x256_8.gds b/verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1rw1r_64x256_8.gds deleted file mode 100755 index 741ec5a..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/macros/gds/sky130_sram_1rw1r_64x256_8.gds +++ /dev/null Binary files differ
diff --git a/verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef b/verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef deleted file mode 100755 index 30b2ff4..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef +++ /dev/null
@@ -1,1093 +0,0 @@ -VERSION 5.4 ; -NAMESCASESENSITIVE ON ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; -UNITS - DATABASE MICRONS 1000 ; -END UNITS -MACRO sky130_sram_1kbyte_1rw1r_32x256_8 - CLASS BLOCK ; - SIZE 479.78 BY 397.5 ; - SYMMETRY X Y R90 ; - PIN din0[0] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 106.76 0.0 107.14 1.06 ; - END - END din0[0] - PIN din0[1] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 112.88 0.0 113.26 1.06 ; - END - END din0[1] - PIN din0[2] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 118.32 0.0 118.7 1.06 ; - END - END din0[2] - PIN din0[3] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 125.12 0.0 125.5 1.06 ; - END - END din0[3] - PIN din0[4] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 130.56 0.0 130.94 1.06 ; - END - END din0[4] - PIN din0[5] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 136.0 0.0 136.38 1.06 ; - END - END din0[5] - PIN din0[6] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 141.44 0.0 141.82 1.06 ; - END - END din0[6] - PIN din0[7] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 148.24 0.0 148.62 1.06 ; - END - END din0[7] - PIN din0[8] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 153.68 0.0 154.06 1.06 ; - END - END din0[8] - PIN din0[9] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 159.12 0.0 159.5 1.06 ; - END - END din0[9] - PIN din0[10] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 165.24 0.0 165.62 1.06 ; - END - END din0[10] - PIN din0[11] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 170.68 0.0 171.06 1.06 ; - END - END din0[11] - PIN din0[12] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 177.48 0.0 177.86 1.06 ; - END - END din0[12] - PIN din0[13] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 182.92 0.0 183.3 1.06 ; - END - END din0[13] - PIN din0[14] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 188.36 0.0 188.74 1.06 ; - END - END din0[14] - PIN din0[15] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 194.48 0.0 194.86 1.06 ; - END - END din0[15] - PIN din0[16] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 201.28 0.0 201.66 1.06 ; - END - END din0[16] - PIN din0[17] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 206.72 0.0 207.1 1.06 ; - END - END din0[17] - PIN din0[18] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 212.16 0.0 212.54 1.06 ; - END - END din0[18] - PIN din0[19] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 217.6 0.0 217.98 1.06 ; - END - END din0[19] - PIN din0[20] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 224.4 0.0 224.78 1.06 ; - END - END din0[20] - PIN din0[21] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 229.84 0.0 230.22 1.06 ; - END - END din0[21] - PIN din0[22] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 235.28 0.0 235.66 1.06 ; - END - END din0[22] - PIN din0[23] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 241.4 0.0 241.78 1.06 ; - END - END din0[23] - PIN din0[24] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 246.84 0.0 247.22 1.06 ; - END - END din0[24] - PIN din0[25] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 253.64 0.0 254.02 1.06 ; - END - END din0[25] - PIN din0[26] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 259.08 0.0 259.46 1.06 ; - END - END din0[26] - PIN din0[27] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 264.52 0.0 264.9 1.06 ; - END - END din0[27] - PIN din0[28] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 269.96 0.0 270.34 1.06 ; - END - END din0[28] - PIN din0[29] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 276.08 0.0 276.46 1.06 ; - END - END din0[29] - PIN din0[30] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 282.88 0.0 283.26 1.06 ; - END - END din0[30] - PIN din0[31] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 288.32 0.0 288.7 1.06 ; - END - END din0[31] - PIN addr0[0] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 77.52 0.0 77.9 1.06 ; - END - END addr0[0] - PIN addr0[1] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 128.52 1.06 128.9 ; - END - END addr0[1] - PIN addr0[2] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 137.36 1.06 137.74 ; - END - END addr0[2] - PIN addr0[3] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 142.12 1.06 142.5 ; - END - END addr0[3] - PIN addr0[4] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 150.28 1.06 150.66 ; - END - END addr0[4] - PIN addr0[5] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 155.72 1.06 156.1 ; - END - END addr0[5] - PIN addr0[6] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 164.56 1.06 164.94 ; - END - END addr0[6] - PIN addr0[7] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 170.68 1.06 171.06 ; - END - END addr0[7] - PIN addr1[0] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 397.12 396.44 397.5 397.5 ; - END - END addr1[0] - PIN addr1[1] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 478.72 82.96 479.78 83.34 ; - END - END addr1[1] - PIN addr1[2] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 478.72 74.8 479.78 75.18 ; - END - END addr1[2] - PIN addr1[3] - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 478.72 68.0 479.78 68.38 ; - END - END addr1[3] - PIN addr1[4] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 415.48 0.0 415.86 1.06 ; - END - END addr1[4] - PIN addr1[5] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 413.44 0.0 413.82 1.06 ; - END - END addr1[5] - PIN addr1[6] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 414.12 0.0 414.5 1.06 ; - END - END addr1[6] - PIN addr1[7] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 414.8 0.0 415.18 1.06 ; - END - END addr1[7] - PIN csb0 - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 27.88 1.06 28.26 ; - END - END csb0 - PIN csb1 - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 478.72 382.16 479.78 382.54 ; - END - END csb1 - PIN web0 - DIRECTION INPUT ; - PORT - LAYER met3 ; - RECT 0.0 36.04 1.06 36.42 ; - END - END web0 - PIN clk0 - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 29.24 0.0 29.62 1.06 ; - END - END clk0 - PIN clk1 - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 450.16 396.44 450.54 397.5 ; - END - END clk1 - PIN wmask0[0] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 83.64 0.0 84.02 1.06 ; - END - END wmask0[0] - PIN wmask0[1] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 89.08 0.0 89.46 1.06 ; - END - END wmask0[1] - PIN wmask0[2] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 95.88 0.0 96.26 1.06 ; - END - END wmask0[2] - PIN wmask0[3] - DIRECTION INPUT ; - PORT - LAYER met4 ; - RECT 100.64 0.0 101.02 1.06 ; - END - END wmask0[3] - PIN dout0[0] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 139.4 0.0 139.78 1.06 ; - END - END dout0[0] - PIN dout0[1] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 146.2 0.0 146.58 1.06 ; - END - END dout0[1] - PIN dout0[2] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 151.64 0.0 152.02 1.06 ; - END - END dout0[2] - PIN dout0[3] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 159.8 0.0 160.18 1.06 ; - END - END dout0[3] - PIN dout0[4] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 165.92 0.0 166.3 1.06 ; - END - END dout0[4] - PIN dout0[5] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 172.04 0.0 172.42 1.06 ; - END - END dout0[5] - PIN dout0[6] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 178.16 0.0 178.54 1.06 ; - END - END dout0[6] - PIN dout0[7] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 184.28 0.0 184.66 1.06 ; - END - END dout0[7] - PIN dout0[8] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 189.04 0.0 189.42 1.06 ; - END - END dout0[8] - PIN dout0[9] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 196.52 0.0 196.9 1.06 ; - END - END dout0[9] - PIN dout0[10] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 203.32 0.0 203.7 1.06 ; - END - END dout0[10] - PIN dout0[11] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 209.44 0.0 209.82 1.06 ; - END - END dout0[11] - PIN dout0[12] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 215.56 0.0 215.94 1.06 ; - END - END dout0[12] - PIN dout0[13] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 221.68 0.0 222.06 1.06 ; - END - END dout0[13] - PIN dout0[14] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 227.8 0.0 228.18 1.06 ; - END - END dout0[14] - PIN dout0[15] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 233.24 0.0 233.62 1.06 ; - END - END dout0[15] - PIN dout0[16] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 239.36 0.0 239.74 1.06 ; - END - END dout0[16] - PIN dout0[17] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 245.48 0.0 245.86 1.06 ; - END - END dout0[17] - PIN dout0[18] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 252.96 0.0 253.34 1.06 ; - END - END dout0[18] - PIN dout0[19] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 257.04 0.0 257.42 1.06 ; - END - END dout0[19] - PIN dout0[20] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 265.88 0.0 266.26 1.06 ; - END - END dout0[20] - PIN dout0[21] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 272.0 0.0 272.38 1.06 ; - END - END dout0[21] - PIN dout0[22] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 278.12 0.0 278.5 1.06 ; - END - END dout0[22] - PIN dout0[23] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 284.24 0.0 284.62 1.06 ; - END - END dout0[23] - PIN dout0[24] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 289.0 0.0 289.38 1.06 ; - END - END dout0[24] - PIN dout0[25] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 296.48 0.0 296.86 1.06 ; - END - END dout0[25] - PIN dout0[26] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 302.6 0.0 302.98 1.06 ; - END - END dout0[26] - PIN dout0[27] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 309.4 0.0 309.78 1.06 ; - END - END dout0[27] - PIN dout0[28] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 315.52 0.0 315.9 1.06 ; - END - END dout0[28] - PIN dout0[29] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 321.64 0.0 322.02 1.06 ; - END - END dout0[29] - PIN dout0[30] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 327.76 0.0 328.14 1.06 ; - END - END dout0[30] - PIN dout0[31] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 333.88 0.0 334.26 1.06 ; - END - END dout0[31] - PIN dout1[0] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 140.76 396.44 141.14 397.5 ; - END - END dout1[0] - PIN dout1[1] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 147.56 396.44 147.94 397.5 ; - END - END dout1[1] - PIN dout1[2] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 153.0 396.44 153.38 397.5 ; - END - END dout1[2] - PIN dout1[3] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 159.8 396.44 160.18 397.5 ; - END - END dout1[3] - PIN dout1[4] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 165.92 396.44 166.3 397.5 ; - END - END dout1[4] - PIN dout1[5] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 172.72 396.44 173.1 397.5 ; - END - END dout1[5] - PIN dout1[6] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 178.84 396.44 179.22 397.5 ; - END - END dout1[6] - PIN dout1[7] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 184.28 396.44 184.66 397.5 ; - END - END dout1[7] - PIN dout1[8] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 191.08 396.44 191.46 397.5 ; - END - END dout1[8] - PIN dout1[9] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 196.52 396.44 196.9 397.5 ; - END - END dout1[9] - PIN dout1[10] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 203.32 396.44 203.7 397.5 ; - END - END dout1[10] - PIN dout1[11] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 209.44 396.44 209.82 397.5 ; - END - END dout1[11] - PIN dout1[12] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 216.24 396.44 216.62 397.5 ; - END - END dout1[12] - PIN dout1[13] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 221.68 396.44 222.06 397.5 ; - END - END dout1[13] - PIN dout1[14] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 227.8 396.44 228.18 397.5 ; - END - END dout1[14] - PIN dout1[15] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 234.6 396.44 234.98 397.5 ; - END - END dout1[15] - PIN dout1[16] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 240.72 396.44 241.1 397.5 ; - END - END dout1[16] - PIN dout1[17] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 247.52 396.44 247.9 397.5 ; - END - END dout1[17] - PIN dout1[18] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 252.96 396.44 253.34 397.5 ; - END - END dout1[18] - PIN dout1[19] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 259.76 396.44 260.14 397.5 ; - END - END dout1[19] - PIN dout1[20] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 265.2 396.44 265.58 397.5 ; - END - END dout1[20] - PIN dout1[21] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 271.32 396.44 271.7 397.5 ; - END - END dout1[21] - PIN dout1[22] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 278.12 396.44 278.5 397.5 ; - END - END dout1[22] - PIN dout1[23] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 284.24 396.44 284.62 397.5 ; - END - END dout1[23] - PIN dout1[24] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 291.04 396.44 291.42 397.5 ; - END - END dout1[24] - PIN dout1[25] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 296.48 396.44 296.86 397.5 ; - END - END dout1[25] - PIN dout1[26] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 303.28 396.44 303.66 397.5 ; - END - END dout1[26] - PIN dout1[27] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 309.4 396.44 309.78 397.5 ; - END - END dout1[27] - PIN dout1[28] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 316.2 396.44 316.58 397.5 ; - END - END dout1[28] - PIN dout1[29] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 321.64 396.44 322.02 397.5 ; - END - END dout1[29] - PIN dout1[30] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 327.76 396.44 328.14 397.5 ; - END - END dout1[30] - PIN dout1[31] - DIRECTION OUTPUT ; - PORT - LAYER met4 ; - RECT 334.56 396.44 334.94 397.5 ; - END - END dout1[31] - PIN vccd1 - DIRECTION INOUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER met4 ; - RECT 473.28 4.76 475.02 392.74 ; - LAYER met4 ; - RECT 4.76 4.76 6.5 392.74 ; - LAYER met3 ; - RECT 4.76 4.76 475.02 6.5 ; - LAYER met3 ; - RECT 4.76 391.0 475.02 392.74 ; - END - END vccd1 - PIN vssd1 - DIRECTION INOUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER met4 ; - RECT 1.36 1.36 3.1 396.14 ; - LAYER met3 ; - RECT 1.36 394.4 478.42 396.14 ; - LAYER met3 ; - RECT 1.36 1.36 478.42 3.1 ; - LAYER met4 ; - RECT 476.68 1.36 478.42 396.14 ; - END - END vssd1 - OBS - LAYER met1 ; - RECT 0.62 0.62 479.16 396.88 ; - LAYER met2 ; - RECT 0.62 0.62 479.16 396.88 ; - LAYER met3 ; - RECT 1.66 127.92 479.16 129.5 ; - RECT 0.62 129.5 1.66 136.76 ; - RECT 0.62 138.34 1.66 141.52 ; - RECT 0.62 143.1 1.66 149.68 ; - RECT 0.62 151.26 1.66 155.12 ; - RECT 0.62 156.7 1.66 163.96 ; - RECT 0.62 165.54 1.66 170.08 ; - RECT 1.66 82.36 478.12 83.94 ; - RECT 1.66 83.94 478.12 127.92 ; - RECT 478.12 83.94 479.16 127.92 ; - RECT 478.12 75.78 479.16 82.36 ; - RECT 478.12 68.98 479.16 74.2 ; - RECT 1.66 129.5 478.12 381.56 ; - RECT 1.66 381.56 478.12 383.14 ; - RECT 478.12 129.5 479.16 381.56 ; - RECT 0.62 28.86 1.66 35.44 ; - RECT 0.62 37.02 1.66 127.92 ; - RECT 1.66 4.16 4.16 7.1 ; - RECT 1.66 7.1 4.16 82.36 ; - RECT 4.16 7.1 475.62 82.36 ; - RECT 475.62 4.16 478.12 7.1 ; - RECT 475.62 7.1 478.12 82.36 ; - RECT 1.66 383.14 4.16 390.4 ; - RECT 1.66 390.4 4.16 393.34 ; - RECT 4.16 383.14 475.62 390.4 ; - RECT 475.62 383.14 478.12 390.4 ; - RECT 475.62 390.4 478.12 393.34 ; - RECT 0.62 171.66 0.76 393.8 ; - RECT 0.62 393.8 0.76 396.74 ; - RECT 0.62 396.74 0.76 396.88 ; - RECT 0.76 171.66 1.66 393.8 ; - RECT 0.76 396.74 1.66 396.88 ; - RECT 478.12 383.14 479.02 393.8 ; - RECT 478.12 396.74 479.02 396.88 ; - RECT 479.02 383.14 479.16 393.8 ; - RECT 479.02 393.8 479.16 396.74 ; - RECT 479.02 396.74 479.16 396.88 ; - RECT 1.66 393.34 4.16 393.8 ; - RECT 1.66 396.74 4.16 396.88 ; - RECT 4.16 393.34 475.62 393.8 ; - RECT 4.16 396.74 475.62 396.88 ; - RECT 475.62 393.34 478.12 393.8 ; - RECT 475.62 396.74 478.12 396.88 ; - RECT 478.12 0.62 479.02 0.76 ; - RECT 478.12 3.7 479.02 67.4 ; - RECT 479.02 0.62 479.16 0.76 ; - RECT 479.02 0.76 479.16 3.7 ; - RECT 479.02 3.7 479.16 67.4 ; - RECT 0.62 0.62 0.76 0.76 ; - RECT 0.62 0.76 0.76 3.7 ; - RECT 0.62 3.7 0.76 27.28 ; - RECT 0.76 0.62 1.66 0.76 ; - RECT 0.76 3.7 1.66 27.28 ; - RECT 1.66 0.62 4.16 0.76 ; - RECT 1.66 3.7 4.16 4.16 ; - RECT 4.16 0.62 475.62 0.76 ; - RECT 4.16 3.7 475.62 4.16 ; - RECT 475.62 0.62 478.12 0.76 ; - RECT 475.62 3.7 478.12 4.16 ; - LAYER met4 ; - RECT 106.16 1.66 107.74 396.88 ; - RECT 107.74 0.62 112.28 1.66 ; - RECT 113.86 0.62 117.72 1.66 ; - RECT 119.3 0.62 124.52 1.66 ; - RECT 126.1 0.62 129.96 1.66 ; - RECT 131.54 0.62 135.4 1.66 ; - RECT 154.66 0.62 158.52 1.66 ; - RECT 260.06 0.62 263.92 1.66 ; - RECT 107.74 1.66 396.52 395.84 ; - RECT 396.52 1.66 398.1 395.84 ; - RECT 30.22 0.62 76.92 1.66 ; - RECT 398.1 395.84 449.56 396.88 ; - RECT 78.5 0.62 83.04 1.66 ; - RECT 84.62 0.62 88.48 1.66 ; - RECT 90.06 0.62 95.28 1.66 ; - RECT 96.86 0.62 100.04 1.66 ; - RECT 101.62 0.62 106.16 1.66 ; - RECT 136.98 0.62 138.8 1.66 ; - RECT 140.38 0.62 140.84 1.66 ; - RECT 142.42 0.62 145.6 1.66 ; - RECT 147.18 0.62 147.64 1.66 ; - RECT 149.22 0.62 151.04 1.66 ; - RECT 152.62 0.62 153.08 1.66 ; - RECT 160.78 0.62 164.64 1.66 ; - RECT 166.9 0.62 170.08 1.66 ; - RECT 173.02 0.62 176.88 1.66 ; - RECT 179.14 0.62 182.32 1.66 ; - RECT 185.26 0.62 187.76 1.66 ; - RECT 190.02 0.62 193.88 1.66 ; - RECT 195.46 0.62 195.92 1.66 ; - RECT 197.5 0.62 200.68 1.66 ; - RECT 202.26 0.62 202.72 1.66 ; - RECT 204.3 0.62 206.12 1.66 ; - RECT 207.7 0.62 208.84 1.66 ; - RECT 210.42 0.62 211.56 1.66 ; - RECT 213.14 0.62 214.96 1.66 ; - RECT 216.54 0.62 217.0 1.66 ; - RECT 218.58 0.62 221.08 1.66 ; - RECT 222.66 0.62 223.8 1.66 ; - RECT 225.38 0.62 227.2 1.66 ; - RECT 228.78 0.62 229.24 1.66 ; - RECT 230.82 0.62 232.64 1.66 ; - RECT 234.22 0.62 234.68 1.66 ; - RECT 236.26 0.62 238.76 1.66 ; - RECT 240.34 0.62 240.8 1.66 ; - RECT 242.38 0.62 244.88 1.66 ; - RECT 247.82 0.62 252.36 1.66 ; - RECT 254.62 0.62 256.44 1.66 ; - RECT 258.02 0.62 258.48 1.66 ; - RECT 266.86 0.62 269.36 1.66 ; - RECT 270.94 0.62 271.4 1.66 ; - RECT 272.98 0.62 275.48 1.66 ; - RECT 277.06 0.62 277.52 1.66 ; - RECT 279.1 0.62 282.28 1.66 ; - RECT 285.22 0.62 287.72 1.66 ; - RECT 289.98 0.62 295.88 1.66 ; - RECT 297.46 0.62 302.0 1.66 ; - RECT 303.58 0.62 308.8 1.66 ; - RECT 310.38 0.62 314.92 1.66 ; - RECT 316.5 0.62 321.04 1.66 ; - RECT 322.62 0.62 327.16 1.66 ; - RECT 328.74 0.62 333.28 1.66 ; - RECT 334.86 0.62 412.84 1.66 ; - RECT 107.74 395.84 140.16 396.88 ; - RECT 141.74 395.84 146.96 396.88 ; - RECT 148.54 395.84 152.4 396.88 ; - RECT 153.98 395.84 159.2 396.88 ; - RECT 160.78 395.84 165.32 396.88 ; - RECT 166.9 395.84 172.12 396.88 ; - RECT 173.7 395.84 178.24 396.88 ; - RECT 179.82 395.84 183.68 396.88 ; - RECT 185.26 395.84 190.48 396.88 ; - RECT 192.06 395.84 195.92 396.88 ; - RECT 197.5 395.84 202.72 396.88 ; - RECT 204.3 395.84 208.84 396.88 ; - RECT 210.42 395.84 215.64 396.88 ; - RECT 217.22 395.84 221.08 396.88 ; - RECT 222.66 395.84 227.2 396.88 ; - RECT 228.78 395.84 234.0 396.88 ; - RECT 235.58 395.84 240.12 396.88 ; - RECT 241.7 395.84 246.92 396.88 ; - RECT 248.5 395.84 252.36 396.88 ; - RECT 253.94 395.84 259.16 396.88 ; - RECT 260.74 395.84 264.6 396.88 ; - RECT 266.18 395.84 270.72 396.88 ; - RECT 272.3 395.84 277.52 396.88 ; - RECT 279.1 395.84 283.64 396.88 ; - RECT 285.22 395.84 290.44 396.88 ; - RECT 292.02 395.84 295.88 396.88 ; - RECT 297.46 395.84 302.68 396.88 ; - RECT 304.26 395.84 308.8 396.88 ; - RECT 310.38 395.84 315.6 396.88 ; - RECT 317.18 395.84 321.04 396.88 ; - RECT 322.62 395.84 327.16 396.88 ; - RECT 328.74 395.84 333.96 396.88 ; - RECT 335.54 395.84 396.52 396.88 ; - RECT 398.1 1.66 472.68 4.16 ; - RECT 398.1 4.16 472.68 393.34 ; - RECT 398.1 393.34 472.68 395.84 ; - RECT 472.68 1.66 475.62 4.16 ; - RECT 472.68 393.34 475.62 395.84 ; - RECT 4.16 1.66 7.1 4.16 ; - RECT 4.16 393.34 7.1 396.88 ; - RECT 7.1 1.66 106.16 4.16 ; - RECT 7.1 4.16 106.16 393.34 ; - RECT 7.1 393.34 106.16 396.88 ; - RECT 0.62 0.62 0.76 0.76 ; - RECT 0.62 0.76 0.76 1.66 ; - RECT 0.76 0.62 3.7 0.76 ; - RECT 3.7 0.62 28.64 0.76 ; - RECT 3.7 0.76 28.64 1.66 ; - RECT 0.62 1.66 0.76 4.16 ; - RECT 3.7 1.66 4.16 4.16 ; - RECT 0.62 4.16 0.76 393.34 ; - RECT 3.7 4.16 4.16 393.34 ; - RECT 0.62 393.34 0.76 396.74 ; - RECT 0.62 396.74 0.76 396.88 ; - RECT 0.76 396.74 3.7 396.88 ; - RECT 3.7 393.34 4.16 396.74 ; - RECT 3.7 396.74 4.16 396.88 ; - RECT 416.46 0.62 476.08 0.76 ; - RECT 416.46 0.76 476.08 1.66 ; - RECT 476.08 0.62 479.02 0.76 ; - RECT 479.02 0.62 479.16 0.76 ; - RECT 479.02 0.76 479.16 1.66 ; - RECT 451.14 395.84 476.08 396.74 ; - RECT 451.14 396.74 476.08 396.88 ; - RECT 476.08 396.74 479.02 396.88 ; - RECT 479.02 395.84 479.16 396.74 ; - RECT 479.02 396.74 479.16 396.88 ; - RECT 475.62 1.66 476.08 4.16 ; - RECT 479.02 1.66 479.16 4.16 ; - RECT 475.62 4.16 476.08 393.34 ; - RECT 479.02 4.16 479.16 393.34 ; - RECT 475.62 393.34 476.08 395.84 ; - RECT 479.02 393.34 479.16 395.84 ; - END -END sky130_sram_1kbyte_1rw1r_32x256_8 -END LIBRARY
diff --git a/verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1rw1r_64x256_8.lef b/verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1rw1r_64x256_8.lef deleted file mode 100755 index bd72971..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/macros/lef/sky130_sram_1rw1r_64x256_8.lef +++ /dev/null Binary files differ
diff --git a/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v deleted file mode 100755 index 9633856..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v +++ /dev/null
@@ -1,111 +0,0 @@ -// OpenRAM SRAM model -// Words: 256 -// Word size: 32 -// Write size: 8 -/* verilator lint_off UNUSED */ -/* verilator lint_off MULTIDRIVEN */ -module sky130_sram_1kbyte_1rw1r_32x256_8( -`ifdef USE_POWER_PINS - vccd1, - vssd1, -`endif -// Port 0: RW - clk0,csb0,web0,wmask0,addr0,din0,dout0, -// Port 1: R - clk1,csb1,addr1,dout1 - ); - - parameter NUM_WMASKS = 4 ; - parameter DATA_WIDTH = 32 ; - parameter ADDR_WIDTH = 8 ; - parameter RAM_DEPTH = 1 << ADDR_WIDTH; - // FIXME: This delay is arbitrary. - parameter DELAY = 3 ; - parameter VERBOSE = 1 ; //Set to 0 to only display warnings - parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary - -`ifdef USE_POWER_PINS - inout vccd1; - inout vssd1; -`endif - input clk0; // clock - input csb0; // active low chip select - input web0; // active low write control - input [NUM_WMASKS-1:0] wmask0; // write mask - input [ADDR_WIDTH-1:0] addr0; - input [DATA_WIDTH-1:0] din0; - output [DATA_WIDTH-1:0] dout0; - input clk1; // clock - input csb1; // active low chip select - input [ADDR_WIDTH-1:0] addr1; - output [DATA_WIDTH-1:0] dout1; - - reg csb0_reg; - reg web0_reg; - reg [NUM_WMASKS-1:0] wmask0_reg; - reg [ADDR_WIDTH-1:0] addr0_reg; - reg [DATA_WIDTH-1:0] din0_reg; - reg [DATA_WIDTH-1:0] dout0; - reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - // All inputs are registers - always @(posedge clk0) - begin - csb0_reg <= csb0; - web0_reg <= web0; - wmask0_reg <= wmask0; - addr0_reg <= addr0; - din0_reg <= din0; - - // if ( !csb0_reg && web0_reg && VERBOSE ) - // $display($time," Reading %m addr0=%x dout0=%b",addr0_reg,mem[addr0_reg]); - // if ( !csb0_reg && !web0_reg && VERBOSE ) - // $display($time," Writing %m addr0=%x din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); - end - - reg csb1_reg; - reg [ADDR_WIDTH-1:0] addr1_reg; - reg [DATA_WIDTH-1:0] dout1; - - // All inputs are registers - always @(posedge clk1) - begin - csb1_reg <= csb1; - addr1_reg <= addr1; - end - - - - // Memory Write Block Port 0 - // Write Operation : When web0 = 0, csb0 = 0 - always @ (negedge clk0) - begin : MEM_WRITE0 - if ( !csb0_reg && !web0_reg ) begin - if (wmask0_reg[0]) - mem[addr0_reg][7:0] <= din0_reg[7:0]; - if (wmask0_reg[1]) - mem[addr0_reg][15:8] <= din0_reg[15:8]; - if (wmask0_reg[2]) - mem[addr0_reg][23:16] <= din0_reg[23:16]; - if (wmask0_reg[3]) - mem[addr0_reg][31:24] <= din0_reg[31:24]; - end - end - - // Memory Read Block Port 0 - // Read Operation : When web0 = 1, csb0 = 0 - always @ (negedge clk0) - begin : MEM_READ0 - if (!csb0_reg && web0_reg) - dout0 <= #(DELAY) mem[addr0_reg]; - end - - // Memory Read Block Port 1 - // Read Operation : When web1 = 1, csb1 = 0 - always @ (negedge clk1) - begin : MEM_READ1 - if (!csb1_reg) - dout1 <= #(DELAY) mem[addr1_reg]; - end -/* verilator lint_on UNUSED */ -endmodule -
diff --git a/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1rw1r_64x256_8.v b/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1rw1r_64x256_8.v deleted file mode 100755 index 072e129..0000000 --- a/verilog/rtl_sram_out_cache/hehe/src/macros/verilog/sky130_sram_1rw1r_64x256_8.v +++ /dev/null
@@ -1,119 +0,0 @@ -// OpenRAM SRAM model -// Words: 256 -// Word size: 64 -// Write size: 8 - -/* verilator lint_off MULTIDRIVEN */ -/* verilator lint_off UNUSED */ -module sky130_sram_1rw1r_64x256_8( -// Port 0: RW - clk0,csb0,web0,wmask0,addr0,din0,dout0, -// Port 1: R - clk1,csb1,addr1,dout1 - ); - - parameter NUM_WMASKS = 8 ; - parameter DATA_WIDTH = 64 ; - parameter ADDR_WIDTH = 8 ; - parameter RAM_DEPTH = 1 << ADDR_WIDTH; - // FIXME: This delay is arbitrary. - parameter DELAY = 3 ; - parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary - input clk0; // clock - input csb0; // active low chip select - input web0; // active low write control - input [NUM_WMASKS-1:0] wmask0; // write mask - input [ADDR_WIDTH-1:0] addr0; - input [DATA_WIDTH-1:0] din0; - output [DATA_WIDTH-1:0] dout0; - input clk1; // clock - input csb1; // active low chip select - input [ADDR_WIDTH-1:0] addr1; - output [DATA_WIDTH-1:0] dout1; - - reg csb0_reg; - reg web0_reg; - reg [NUM_WMASKS-1:0] wmask0_reg; - reg [ADDR_WIDTH-1:0] addr0_reg; - reg [DATA_WIDTH-1:0] din0_reg; - reg [DATA_WIDTH-1:0] dout0; - reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - // All inputs are registers - always @(posedge clk0) - begin - csb0_reg <= csb0; - web0_reg <= web0; - wmask0_reg <= wmask0; - addr0_reg <= addr0; - din0_reg <= din0; - /*verilator lint_off STMTDLY*/ - //#(T_HOLD) dout0 <= 64'bx; - // if ( !csb0_reg && web0_reg ) - // $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); - // if ( !csb0_reg && !web0_reg ) - // $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg); - /*verilator lint_on STMTDLY*/ - end - - reg csb1_reg; - reg [ADDR_WIDTH-1:0] addr1_reg; - reg [DATA_WIDTH-1:0] dout1; - - // All inputs are registers - always @(posedge clk1) - begin - csb1_reg <= csb1; - addr1_reg <= addr1; -// if (!csb0 && !web0 && !csb1 && (addr0 == addr1)) -// $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1); - // dout1 <= 64'bx; -// if ( !csb1_reg ) -// $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]); - end - - - - // Memory Write Block Port 0 - // Write Operation : When web0 = 0, csb0 = 0 - always @ (negedge clk0) - begin : MEM_WRITE0 - if ( !csb0_reg && !web0_reg ) begin - if (wmask0_reg[0]) - mem[addr0_reg][7:0] <= din0_reg[7:0]; - if (wmask0_reg[1]) - mem[addr0_reg][15:8] <= din0_reg[15:8]; - if (wmask0_reg[2]) - mem[addr0_reg][23:16] <= din0_reg[23:16]; - if (wmask0_reg[3]) - mem[addr0_reg][31:24] <= din0_reg[31:24]; - if (wmask0_reg[4]) - mem[addr0_reg][39:32] <= din0_reg[39:32]; - if (wmask0_reg[5]) - mem[addr0_reg][47:40] <= din0_reg[47:40]; - if (wmask0_reg[6]) - mem[addr0_reg][55:48] <= din0_reg[55:48]; - if (wmask0_reg[7]) - mem[addr0_reg][63:56] <= din0_reg[63:56]; - end - end - - // Memory Read Block Port 0 - // Read Operation : When web0 = 1, csb0 = 0 - always @ (negedge clk0) - begin : MEM_READ0 - if (!csb0_reg && web0_reg) - /*verilator lint_off ASSIGNDLY*/ - dout0 <= #(DELAY) mem[addr0_reg]; - - end - - // Memory Read Block Port 1 - // Read Operation : When web1 = 1, csb1 = 0 - always @ (negedge clk1) - begin : MEM_READ1 - if (!csb1_reg) - dout1 <= #(DELAY) mem[addr1_reg]; - end - -endmodule - /*verilator lint_on ASSIGNDLY*/
diff --git a/verilog/rtl_sram_out_cache/hehe/src/params.vh b/verilog/rtl_sram_out_cache/hehe/src/params.vh index b8deb41..99cb6d2 100755 --- a/verilog/rtl_sram_out_cache/hehe/src/params.vh +++ b/verilog/rtl_sram_out_cache/hehe/src/params.vh
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 `ifndef PARAMS_VH `define PARAMS_VH // MACROS
diff --git a/verilog/rtl_sram_out_cache/latch_map.v b/verilog/rtl_sram_out_cache/latch_map.v index 03f3ca0..56813ec 100644 --- a/verilog/rtl_sram_out_cache/latch_map.v +++ b/verilog/rtl_sram_out_cache/latch_map.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 RIOSLab +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 module \$_DLATCH_P_ (input E, input D, output Q); gf180mcu_fd_sc_mcu7t5v0__latq_1 _TECHMAP_DLATCH_P ( //# {{data|Data Signals}}
diff --git a/verilog/rtl_sram_out_cache/top.v b/verilog/rtl_sram_out_cache/top.v index e5d0afe..53a36cd 100755 --- a/verilog/rtl_sram_out_cache/top.v +++ b/verilog/rtl_sram_out_cache/top.v
@@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation +// SPDX-FileCopyrightText: 2022 RIOS Lab // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License.