commit	347717843ca1b5b794153a3822a27dd5daebd7f2	[log] [tgz]
author	Ruige <295054118@whut.edu.cn>	Sat Dec 03 01:34:49 2022 +0800
committer	Ruige <295054118@whut.edu.cn>	Sat Dec 03 01:34:49 2022 +0800
tree	e3540ff79949dc4bc451e0fb9a1041915a68012a
parent	6b905e71661e4c3760eb938145745ecd82222a14 [diff]

upload files

Signed-off-by: Ruige <295054118@whut.edu.cn>

Makefile[diff]
README.md[diff]
def/rift2Wrap.def[Added - diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
gds/rift2Wrap.gds.gz[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/rift2Wrap.lef[Added - diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
lib/rift2Wrap.lib[Added - diff]
lib/user_proj_example.lib[diff]
lib/user_project_wrapper.lib[diff]
mag/rift2Wrap.mag[Added - diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/rift2Wrap.mag[Added - diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
sdc/rift2Wrap.sdc[Added - diff]
sdc/user_proj_example.sdc[diff]
sdc/user_project_wrapper.sdc[diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf[diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf[diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf[diff]
sdf/rift2Wrap.sdf[Added - diff]
sdf/user_proj_example.sdf[diff]
sdf/user_project_wrapper.sdf[diff]
signoff/user_proj_example/metrics.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/metrics.csv[diff]
spef/multicorner/user_project_wrapper.nom.spef[diff]
spef/rift2Wrap.spef[Added - diff]
spef/user_proj_example.spef[diff]
spef/user_project_wrapper.spef[diff]
spi/lvs/rift2Wrap.spice[Added - diff]
spi/lvs/user_proj_example.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/gl/rift2Wrap.nl.v[Added - diff]
verilog/gl/rift2Wrap.v[Added - diff]
verilog/gl/user_proj_example.nl.v[Added - diff]
verilog/gl/user_proj_example.v[diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]

47 files changed

tree: e3540ff79949dc4bc451e0fb9a1041915a68012a

README.md

Rift2Fake

Attention

A Fake Code “LFSR16” is Uploaded.

LFSR

A LFSR16 is instance, it will output four ramdom code in HEX to io. It will be connected to 7-segment seconds and display 4 numbers. A IO can lock the LFSR, it will be connect to a switch.