Sign in
foss-eda-tools
/
third_party
/
shuttle
/
gf180mcu
/
mpw-000
/
slot-015
/
6b905e71661e4c3760eb938145745ecd82222a14
commit
6b905e71661e4c3760eb938145745ecd82222a14
[
log
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author
Ruige <295054118@whut.edu.cn>
Thu Dec 01 19:28:28 2022 +0800
committer
Ruige <295054118@whut.edu.cn>
Thu Dec 01 19:28:28 2022 +0800
tree
ecb88057888540239069d69508c482741d8e15b3
parent
17bbec35943e3072832f66aaa683693d95c21227
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upload fake design files
Makefile
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openlane/user_proj_example/config.tcl
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openlane/user_proj_example/pin_order.cfg
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openlane/user_project_wrapper/config.tcl
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openlane/user_project_wrapper/macro.cfg
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openlane/user_project_wrapper/pin_order.cfg
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verilog/rtl/Sky130BLFSR.v
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verilog/rtl/rift2Fake.v
[Added -
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verilog/rtl/user_defines.v
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verilog/rtl/user_proj_example.v
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verilog/rtl/user_project_wrapper.v
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11 files changed
tree: ecb88057888540239069d69508c482741d8e15b3
.github/
def/
docs/
gds/
lef/
lib/
mag/
maglef/
openlane/
sdc/
sdf/
signoff/
spef/
spi/
verilog/
.gitignore
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.
