Google Git
Sign in
foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-014 / 9e216674ab1b8843e5fd596399c1757df7b4a963 / . / verilog / rtl
tree: e9a9e22768248ba7e946be6833fbfdfefc36d6ca [path history] [tgz]
  1. alu.v
  2. async_ram.v
  3. bin2v.py
  4. boy.v
  5. brom.v
  6. chip.v
  7. clk_div.v
  8. common.v
  9. control.v
  10. cpu.v
  11. defines.v
  12. dma.v
  13. edgedet.v
  14. lfsr.v
  15. lfsr_prbs_gen.v
  16. mbc5.v
  17. ppu.v
  18. README.md
  19. regfile.v
  20. sdm1b.v
  21. serial.v
  22. simtop.v
  23. singleport_ram.v
  24. singlereg.v
  25. sound.v
  26. sound_channel_mix.v
  27. sound_length_ctr.v
  28. sound_noise.v
  29. sound_square.v
  30. sound_vol_env.v
  31. sound_wave.v
  32. timer.v
  33. uprj_netlists.v
  34. user_defines.v
  35. user_proj_example.v
  36. user_project_wrapper.v
verilog/rtl/README.md

Memory Access / Multiplexing

Due to limited pins, cartridge/ main memory access and VRAM access are multiplexed over one same bus.

4-cycles are divided as follows:

  • 0: Cartridge address setup (for external latching)
  • 1: VRAM access
  • 2: WRAM or cartridge RW
  • 3: VRAM access

Diagram:

CT       |  0  |  1  |  2  |  3  |
          ___________             ___            
CLK  ____|           |___________|     
     _    __    __    __    __    __    
CK    |__|  |__|  |__|  |__|  |__|  |
     ____       _____________________
EALE     |_____|
                      _____
ECS  ________________|     |_________
     ________________       _________
WR                   |_____|
     ____ _____ _____ _____ _____ ___
ADDR ____X_WR__X_VR1_X_WR__X_VR2_X___
     ____       _____ _____ _____ 
DATA ____>-----<_VR1_X_WR__X_VR2_>---

Note that VRAM/WRAM seperation is based on function unit: Only PPU accesses VRAM on cycle 2 and 4. If CPU accesses VRAM, it would still happen on cycle 3.