First itterations that:
- Changed config.json back to config.tcl
- Incorprated the new changes done in caravel configuration
- New template def file
- Default configuration is specific for gf180mcuC
- Fixed user_project_wrapper and example rtl verilog to be the same as
the on in caravel
TODO:
- reharden user_project_wrapper in caravel with new OpenLane as the via
insertion is different and will cause an issue with XOR
- Make the repo usable for multiple technologies
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 26081e9..78cd884 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -39,8 +39,8 @@
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
- inout vccd1, // User area 1 1.8V supply
- inout vssd1, // User area 1 digital ground
+ inout vdd, // User area 1 1.8V supply
+ inout vss, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
@@ -56,9 +56,9 @@
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
+ input [63:0] la_data_in,
+ output [63:0] la_data_out,
+ input [63:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
