First itterations that:
- Changed config.json back to config.tcl
- Incorprated the new changes done in caravel configuration
- New template def file
- Default configuration is specific for gf180mcuC
- Fixed user_project_wrapper and example rtl verilog to be the same as
the on in caravel
TODO:
- reharden user_project_wrapper in caravel with new OpenLane as the via
insertion is different and will cause an issue with XOR
- Make the repo usable for multiple technologies
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 26081e9..78cd884 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -39,8 +39,8 @@
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
- inout vccd1, // User area 1 1.8V supply
- inout vssd1, // User area 1 digital ground
+ inout vdd, // User area 1 1.8V supply
+ inout vss, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
@@ -56,9 +56,9 @@
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
+ input [63:0] la_data_in,
+ output [63:0] la_data_out,
+ input [63:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..146877d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -31,16 +31,10 @@
module user_project_wrapper #(
parameter BITS = 32
-) (
+)(
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
+ inout vdd, // User area 5.0V supply
+ inout vss, // User area ground
`endif
// Wishbone Slave ports (WB MI A)
@@ -56,21 +50,15 @@
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
+ input [63:0] la_data_in,
+ output [63:0] la_data_out,
+ input [63:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
- // Analog (direct connection to GPIO pad---use with caution)
- // Note that analog I/O is not available on the 7 lowest-numbered
- // GPIO pads, and so the analog_io indexing is offset from the
- // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
- inout [`MPRJ_IO_PADS-10:0] analog_io,
-
// Independent clock (on independent integer divider)
input user_clock2,
@@ -84,8 +72,8 @@
user_proj_example mprj (
`ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
+ .vdd(vdd), // User area 1 1.8V power
+ .vss(vss), // User area 1 digital ground
`endif
.wb_clk_i(wb_clk_i),
