AllORNothing...
diff --git a/.gitignore b/.gitignore index a853984..8ad6744 100644 --- a/.gitignore +++ b/.gitignore
@@ -6,5 +6,5 @@ *.lst *.vcd *.gtkw -venv +venv/ mgmt_core_wrapper/
diff --git a/openlane/user_BinMult/config.tcl b/openlane/user_BinMult/config.tcl deleted file mode 100644 index ac3a931..0000000 --- a/openlane/user_BinMult/config.tcl +++ /dev/null
@@ -1,59 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "gf180mcuC" -set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" - -set ::env(DESIGN_NAME) BinMultiplier - -## Source Verilog Files -set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/BinMult/BinMultiplier.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "clk" -set ::env(CLOCK_NET) "clk" -set ::env(CLOCK_PERIOD) "50.0" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 400 200" - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.45 - -set ::env(FP_CORE_UTIL) 40 - -set ::env(CLOCK_BUFFER_FANOUT) 16 -set ::env(SYNTH_MAX_FANOUT) 8 -set ::env(SYNTH_BUFFERING) 1 -set ::env(ROUTING_CORES) 8 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -set ::env(RT_MAX_LAYER) {Metal4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vdd}] -set ::env(GND_NETS) [list {vss}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1 \ No newline at end of file
diff --git a/openlane/user_BinMult/pin_order.cfg b/openlane/user_BinMult/pin_order.cfg deleted file mode 100644 index 712dba0..0000000 --- a/openlane/user_BinMult/pin_order.cfg +++ /dev/null
@@ -1,18 +0,0 @@ -#BUS_SORT - -#S -clk -rst -enable -done -dba.* -dbb.* - -#N -Y.* - -#E -yA.* - -#W -yB.*
diff --git a/openlane/user_DiffDigota/config.tcl b/openlane/user_DiffDigota/config.tcl deleted file mode 100644 index 7709b05..0000000 --- a/openlane/user_DiffDigota/config.tcl +++ /dev/null
@@ -1,57 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "gf180mcuC" -set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" - -set ::env(DESIGN_NAME) DiffDigota - -set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DiffDigota.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "" -set ::env(CLOCK_NET) "" -set ::env(CLOCK_TREE_SYNTH) 0 -set ::env(RUN_SIMPLE_CTS) 0 -set ::env(CLOCK_PERIOD) "24.0" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 80 80" - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.45 - -set ::env(FP_CORE_UTIL) 40 - -set ::env(SYNTH_MAX_FANOUT) 4 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -set ::env(RT_MAX_LAYER) {Metal4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vdd}] -set ::env(GND_NETS) [list {vss}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1 \ No newline at end of file
diff --git a/openlane/user_DiffDigota/pin_order.cfg b/openlane/user_DiffDigota/pin_order.cfg deleted file mode 100644 index c4e14cd..0000000 --- a/openlane/user_DiffDigota/pin_order.cfg +++ /dev/null
@@ -1,18 +0,0 @@ -#BUS_SORT - -#S -INpb -INmb -OUTp -OUTm -oe - -#N -oppmos -opnmos -ompmos -omnmos - -#W -cmpmos -cmnmos
diff --git a/openlane/user_Digota/config.tcl b/openlane/user_Digota/config.tcl deleted file mode 100644 index 01dcbd8..0000000 --- a/openlane/user_Digota/config.tcl +++ /dev/null
@@ -1,57 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "gf180mcuC" -set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" - -set ::env(DESIGN_NAME) DIGOTA - -set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DIGOTA.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "" -set ::env(CLOCK_NET) "" -set ::env(CLOCK_TREE_SYNTH) 0 -set ::env(RUN_SIMPLE_CTS) 0 -set ::env(CLOCK_PERIOD) "24.0" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 50 50" - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.45 - -set ::env(FP_CORE_UTIL) 40 - -set ::env(SYNTH_MAX_FANOUT) 4 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -set ::env(RT_MAX_LAYER) {Metal4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vdd}] -set ::env(GND_NETS) [list {vss}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1 \ No newline at end of file
diff --git a/openlane/user_Digota/pin_order.cfg b/openlane/user_Digota/pin_order.cfg deleted file mode 100644 index fc966df..0000000 --- a/openlane/user_Digota/pin_order.cfg +++ /dev/null
@@ -1,14 +0,0 @@ -#BUS_SORT - -#S -INpb -INmb -oe - -#N -opmos -onmos - -#W -cmpmos -cmnmos
diff --git a/openlane/user_WaveTbl/config.tcl b/openlane/user_WaveTbl/config.tcl deleted file mode 100644 index 94d2669..0000000 --- a/openlane/user_WaveTbl/config.tcl +++ /dev/null
@@ -1,64 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "gf180mcuC" -set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" - -set ::env(DESIGN_NAME) WavePWM - -## Source Verilog Files -set ::env(VERILOG_FILES) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WavePWM.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WaveTblCosSin.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WaveTblSig.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/BinMult/BinMultiplier.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "clk" -set ::env(CLOCK_NET) "clk" -set ::env(CLOCK_PERIOD) "50.0" - -#set ::env(FP_SIZING) absolute -#set ::env(DIE_AREA) "0 0 500 500" - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.45 - -set ::env(FP_CORE_UTIL) 40 - -set ::env(CLOCK_BUFFER_FANOUT) 16 -set ::env(SYNTH_MAX_FANOUT) 10 -set ::env(SYNTH_BUFFERING) 1 -set ::env(SYNTH_NO_FLAT) 0 -set ::env(SYNTH_SHARE_RESOURCES) 0 -set ::env(ROUTING_CORES) 8 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -set ::env(RT_MAX_LAYER) {Metal4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vdd}] -set ::env(GND_NETS) [list {vss}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1 \ No newline at end of file
diff --git a/openlane/user_WaveTbl/pin_order.cfg b/openlane/user_WaveTbl/pin_order.cfg deleted file mode 100644 index 1f1530b..0000000 --- a/openlane/user_WaveTbl/pin_order.cfg +++ /dev/null
@@ -1,12 +0,0 @@ -#BUS_SORT - -#S -clk -rst -enable -divSel.* - -#N -qcos -qsin -qcomplex
diff --git a/openlane/user_clkgate/config.tcl b/openlane/user_clkgate/config.tcl deleted file mode 100644 index aab424c..0000000 --- a/openlane/user_clkgate/config.tcl +++ /dev/null
@@ -1,59 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "gf180mcuC" -set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" - -set ::env(DESIGN_NAME) clkgate - -set ::env(VERILOG_FILES) "\ - $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkgate.v" - -# Latch mapping -set ::env(SYNTH_LATCH_MAP) "$::env(DESIGN_DIR)/../../verilog/rtl/yosysStdCell/latch_map.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "gclk" -set ::env(CLOCK_NET) "gclk" -set ::env(CLOCK_PERIOD) "24.0" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 60 60" - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.45 - -set ::env(FP_CORE_UTIL) 40 - -set ::env(SYNTH_MAX_FANOUT) 4 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -set ::env(RT_MAX_LAYER) {Metal4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vdd}] -set ::env(GND_NETS) [list {vss}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1 \ No newline at end of file
diff --git a/openlane/user_clkgate/pin_order.cfg b/openlane/user_clkgate/pin_order.cfg deleted file mode 100644 index 68fab08..0000000 --- a/openlane/user_clkgate/pin_order.cfg +++ /dev/null
@@ -1,10 +0,0 @@ -#BUS_SORT - -#S -clk - -#W -gate - -#N -gclk
diff --git a/openlane/user_clkmux2/config.tcl b/openlane/user_clkmux2/config.tcl deleted file mode 100644 index f4c2b4f..0000000 --- a/openlane/user_clkmux2/config.tcl +++ /dev/null
@@ -1,56 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "gf180mcuC" -set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0" - -set ::env(DESIGN_NAME) clkmux2 - -set ::env(VERILOG_FILES) "\ - $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkmux2.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "gclk" -set ::env(CLOCK_NET) "gclk" -set ::env(CLOCK_PERIOD) "24.0" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 80 80" - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.45 - -set ::env(FP_CORE_UTIL) 40 - -set ::env(SYNTH_MAX_FANOUT) 4 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -set ::env(RT_MAX_LAYER) {Metal4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vdd}] -set ::env(GND_NETS) [list {vss}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1 \ No newline at end of file
diff --git a/openlane/user_clkmux2/pin_order.cfg b/openlane/user_clkmux2/pin_order.cfg deleted file mode 100644 index fe030dd..0000000 --- a/openlane/user_clkmux2/pin_order.cfg +++ /dev/null
@@ -1,11 +0,0 @@ -#BUS_SORT - -#S -clka -clkb - -#W -select - -#N -gclk
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl index e6b0789..83cf365 100644 --- a/openlane/user_proj_example/config.tcl +++ b/openlane/user_proj_example/config.tcl
@@ -21,16 +21,28 @@ set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $::env(DESIGN_DIR)/../../verilog/rtl/Wishbone/WishboneSlave.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/defines.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DiffDigota.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DIGOTA.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkgate.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkmux2.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WavePWM.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WaveTblCosSin.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WaveTblSig.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/BinMult/BinMultiplier.v \ $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v" +# Latch mapping +set ::env(SYNTH_LATCH_MAP) "$::env(DESIGN_DIR)/../../verilog/rtl/yosysStdCell/latch_map.v" + set ::env(DESIGN_IS_CORE) 0 set ::env(CLOCK_PORT) "wb_clk_i" set ::env(CLOCK_NET) "clk" set ::env(CLOCK_PERIOD) "24.0" -#set ::env(FP_SIZING) absolute -#set ::env(DIE_AREA) "0 0 900 600" +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 1000 1000" set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg @@ -41,47 +53,6 @@ set ::env(SYNTH_MAX_FANOUT) 4 -### Macro PDN Connections -set ::env(FP_PDN_MACRO_HOOKS) "\ - mprj vdd vss vdd vss" - -### Black-box verilog and views -set ::env(VERILOG_FILES_BLACKBOX) "\ - $::env(DESIGN_DIR)/../../verilog/rtl/defines.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DiffDigota.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/DIGOTA/DIGOTA.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkgate.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/Clocks/clkmux2.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/WaveTbl/WavePWM.v" - -set ::env(EXTRA_LEFS) "\ - $::env(DESIGN_DIR)/../../lef/DiffDigota.lef \ - $::env(DESIGN_DIR)/../../lef/DIGOTA.lef \ - $::env(DESIGN_DIR)/../../lef/clkgate.lef \ - $::env(DESIGN_DIR)/../../lef/clkmux2.lef \ - $::env(DESIGN_DIR)/../../lef/WavePWM.lef" - -set ::env(EXTRA_GDS_FILES) "\ - $::env(DESIGN_DIR)/../../gds/DiffDigota.gds \ - $::env(DESIGN_DIR)/../../gds/DIGOTA.gds \ - $::env(DESIGN_DIR)/../../gds/clkgate.gds \ - $::env(DESIGN_DIR)/../../gds/clkmux2.gds \ - $::env(DESIGN_DIR)/../../gds/WavePWM.gds" - -set ::env(EXTRA_LIBS) "\ - $::env(DESIGN_DIR)/../../lib/DiffDigota.lib \ - $::env(DESIGN_DIR)/../../lib/DIGOTA.lib \ - $::env(DESIGN_DIR)/../../lib/clkgate.lib\ - $::env(DESIGN_DIR)/../../lib/clkmux2.lib\ - $::env(DESIGN_DIR)/../../lib/WavePWM.lib" - -set ::env(RT_MAX_LAYER) {Metal4} - -# disable pdn check nodes becuase it hangs with multiple power domains. -# any issue with pdn connections will be flagged with LVS so it is not a critical check. -set ::env(FP_PDN_CHECK_NODES) 0 - - # Maximum layer used for routing is metal 4. # This is because this macro will be inserted in a top level (user_project_wrapper) # where the PDN is planned on metal 5. So, to avoid having shorts between routes
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg index c671b89..6c15c20 100644 --- a/openlane/user_proj_example/pin_order.cfg +++ b/openlane/user_proj_example/pin_order.cfg
@@ -33,7 +33,7 @@ wbs_.* la_.* user_clock2 -user_irq.* +irq.* #E io_in\[0\]