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foss-eda-tools
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third_party
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shuttle
/
gf180mcu
/
mpw-000
/
slot-013
/
51ab473e5d7666f50a42375bc8aa20258f379c1b
/
.
/
verilog
/
rtl
/
Clocks
/
clkgate.v
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module
clkgate
(
input clk
,
input gate
,
output wire gclk
);
wire clki
=
~
clk
;
reg clkp
;
assign gclk
=
clkp
&
clk
;
always
@*
if
(
clki
)
clkp
<=
gate
;
else
clkp
<=
clkp
;
initial clkp
=
0
;
endmodule