high fanout change
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 71ada0b..b781c22 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -2,7 +2,7 @@
"DESIGN_NAME": "user_proj_example",
"DESIGN_IS_CORE": 0,
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v", "dir::../../verilog/rtl/Minx16/*"],
- "CLOCK_PERIOD": 50,
+ "CLOCK_PERIOD": 10,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "counter.clk, cpu16.clk_i",
"FP_SIZING": "absolute",
@@ -15,6 +15,7 @@
"DIODE_INSERTION_STRATEGY": 4,
"RUN_CVC": 1,
"pdk::sky130*": {
+ "SYNTH_MAX_FANOUT": 5,
"FP_CORE_UTIL": 45,
"RT_MAX_LAYER": "met4",
"scl::sky130_fd_sc_hd": {
diff --git a/verilog/rtl/Minx16/scb.v b/verilog/rtl/Minx16/scb.v
index 598a778..a541d67 100644
--- a/verilog/rtl/Minx16/scb.v
+++ b/verilog/rtl/Minx16/scb.v
@@ -34,15 +34,15 @@
assign scb_Data_o = (highSelect) ? dboh :dbol;
//gf180mcu_fd_ip_sram__sram512x8m8wm1 oddMemLow (
- dfsimpleram #(9, 8) oddMemLow (
- .CLK (clk_i)
- , .CEN (~(oddSelect & lowSelect))
- , .GWEN(~scb_ce_i | scb_wr_i)
- , .WEN (8'h00)
- , .A (addr)
- , .D (dbhi)
- , .Q (dbolo)
- );
+ //dfsimpleram #(9, 8) oddMemLow (
+ // .CLK (clk_i)
+ //, .CEN (~(oddSelect & lowSelect))
+ //, .GWEN(~scb_ce_i | scb_wr_i)
+ //, .WEN (8'h00)
+ //, .A (addr)
+ //, .D (dbhi)
+ //, .Q (dbolo)
+ //);
//gf180mcu_fd_ip_sram__sram512x8m8wm1 oddMemHigh (
dfsimpleram #(9, 8) oddMemHigh (
@@ -56,15 +56,15 @@
);
//gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemLow (
- dfsimpleram #(9, 8) evenMemLow (
- .CLK (clk_i)
- , .CEN (~(evenSelect & lowSelect))
- , .GWEN(~scb_ce_i | scb_wr_i)
- , .WEN (8'h00)
- , .A (addr)
- , .D (dblo)
- , .Q (dbelo)
- );
+ //dfsimpleram #(9, 8) evenMemLow (
+ // .CLK (clk_i)
+ //, .CEN (~(evenSelect & lowSelect))
+ //, .GWEN(~scb_ce_i | scb_wr_i)
+ //, .WEN (8'h00)
+ //, .A (addr)
+ //, .D (dblo)
+ //, .Q (dbelo)
+ //);
//gf180mcu_fd_ip_sram__sram512x8m8wm1 evenMemHigh (
dfsimpleram #(9, 8) evenMemHigh(
