configure: add GPIO_VALID_RANGE
diff --git a/configure.py b/configure.py index 17575a6..1968db4 100755 --- a/configure.py +++ b/configure.py
@@ -11,6 +11,8 @@ import re import jinja2 +GPIO_VALID_RANGE = [8, 36] + def load_yaml(yaml_file): with open(yaml_file, "r") as stream: return (yaml.safe_load(stream)) @@ -121,9 +123,12 @@ else: return yaml['project']['top_module'] -def get_io_ranges(yaml, gpio_base=5): - input_range = (gpio_base, gpio_base+len(yaml['documentation']['inputs'])) +def get_io_ranges(yaml): + input_range = (GPIO_VALID_RANGE[0], GPIO_VALID_RANGE[0]+len(yaml['documentation']['inputs'])) output_range = (input_range[1], input_range[1]+len(yaml['documentation']['outputs'])) + gpio_last = output_range[1] + if gpio_last > GPIO_VALID_RANGE[1]: + raise Exception('ETOOMANY IOs') return (input_range, output_range) def get_stats():
diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json index 3829399..0379a03 100644 --- a/openlane/tiny_user_project/config.json +++ b/openlane/tiny_user_project/config.json
@@ -2,7 +2,7 @@ "DESIGN_NAME": "tiny_user_project", "DESIGN_IS_CORE": 0, "VERILOG_FILES": [ - "dir::../../verilog/rtl/user_module_334445762078310996.v", + "dir::../../verilog/rtl/user_module.v", "dir::../../verilog/rtl/cells.v", "dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/tiny_user_project.v"
diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v index d00e184..0b99eae 100644 --- a/verilog/rtl/tiny_user_project.v +++ b/verilog/rtl/tiny_user_project.v
@@ -12,11 +12,11 @@ // pass input and output pins defined in user_defines.v user_module_334445762078310996 mod ( - io_in[12:5], - io_out[20:13] + io_in[15:8], + io_out[23:16] ); // all output enabled -assign io_oeb[20:13] = 8'b0; +assign io_oeb[23:16] = 8'b0; endmodule // tiny_user_project
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v index c749b72..f65f57b 100644 --- a/verilog/rtl/user_defines.v +++ b/verilog/rtl/user_defines.v
@@ -56,25 +56,25 @@ // generated by configure.py -`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID `define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_OUTPUT `define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_OUTPUT `define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_OUTPUT `define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_OUTPUT `define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_OUTPUT -`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_OUTPUT `define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID `define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID `define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID