openlane/user_module: convert config to json

openlane/user_module/config.json

diff --git a/openlane/user_module/config.json b/openlane/user_module/config.json
new file mode 100644
index 0000000..6b67357
--- /dev/null
+++ b/openlane/user_module/config.json
@@ -0,0 +1,40 @@
+{
+    "DESIGN_NAME": "user_module",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": [
+	"dir::../../verilog/rtl/defines.v",
+	"dir::../../verilog/rtl/cells.v",
+	"dir::../../verilog/rtl/user_module.v"
+    ],
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": "",
+    "CLOCK_NET": "",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 250 250",
+    "FP_CORE_UTIL": 45,
+    "PL_BASIC_PLACEMENT": 1,
+    "PL_TARGET_DENSITY": 0.55,
+    "VDD_NETS": ["vccd1"],
+    "GND_NETS": ["vssd1"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "PL_RESIZER_BUFFER_OUTPUT_PORTS": 0,
+    "SYNTH_READ_BLACKBOX_LIB": 1,
+    "RUN_CVC": 1,
+    "RUN_KLAYOUT_XOR": 0,
+    "RUN_KLAYOUT_DRC": 0,
+    "pdk::sky130*": {
+	"DECAP_CELL": [
+	    "sky130_fd_sc_hd__decap_3",
+	    "sky130_fd_sc_hd__decap_4",
+	    "sky130_fd_sc_hd__decap_6",
+	    "sky130_fd_sc_hd__decap_8",
+	    "sky130_ef_sc_hd__decap_12"
+	],
+        "RT_MAX_LAYER": "met4"
+    },
+    "pdk::gf180mcuC": {
+        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+        "RT_MAX_LAYER": "Metal4",
+        "SYNTH_MAX_FANOUT": 4
+    }
+}

openlane/user_module/config.tcl

diff --git a/openlane/user_module/config.tcl b/openlane/user_module/config.tcl
deleted file mode 100755
index f6e5e24..0000000
--- a/openlane/user_module/config.tcl
+++ /dev/null
@@ -1,62 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# User config
-set script_dir [file dirname [file normalize [info script]]]
-
-# has to match the module name from wokwi
-set ::env(DESIGN_NAME) user_module
-
-# save some time
-set ::env(RUN_KLAYOUT_XOR) 0
-set ::env(RUN_KLAYOUT_DRC) 0
-
-# don't put clock buffers on the outputs
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-
-# allow use of specific sky130 cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-
-# read all verilog files
-set ::env(VERILOG_FILES) "\
-	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/cells.v
-	$script_dir/../../verilog/rtl/user_module.v"
-
-# absolute die size
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 250 250"
-set ::env(FP_CORE_UTIL) 45
-set ::env(PL_BASIC_PLACEMENT) {1}
-
-# use alternative efabless decap cells to solve LI density issue
-set ::env(DECAP_CELL) "\
-    sky130_fd_sc_hd__decap_3 \
-    sky130_fd_sc_hd__decap_4 \
-    sky130_fd_sc_hd__decap_6 \
-    sky130_fd_sc_hd__decap_8 \
-    sky130_ef_sc_hd__decap_12"
-
-# clock
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) ""
-
-# don't use power rings or met5
-set ::env(DESIGN_IS_CORE) 0
-set ::env(RT_MAX_LAYER) {met4}
-
-# connect to first digital rails
-set ::env(VDD_NETS) [list {vccd1}]
-set ::env(GND_NETS) [list {vssd1}]

openlane/user_module/pin_order.cfg

diff --git a/openlane/user_module/pin_order.cfg b/openlane/user_module/pin_order.cfg
new file mode 100644
index 0000000..666737f
--- /dev/null
+++ b/openlane/user_module/pin_order.cfg
@@ -0,0 +1,10 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+irq.*
+
+#N
+io_.*
\ No newline at end of file