mpw_precheck/outputs/reports/klayout_feol_check.xml

<?xml version="1.0" encoding="utf-8"?>
<report-database>
 <description>DRC Run Report at</description>
 <original-file/>
 <generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
 <top-cell>user_project_wrapper</top-cell>
 <tags>
 </tags>
 <categories>
  <category>
   <name>DN.1</name>
   <description>DN.1 : Min. DNWELL Width : 1.7µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DN.2a</name>
   <description>DN.2a : Min. DNWELL Space (Equi-potential), Merge if the space is less than : 2.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DN.2b</name>
   <description>DN.2b : Min. DNWELL Space (Different potential) : 5.42µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DN.3</name>
   <description>DN.3 : Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.1_3.3V</name>
   <description>LPW.1_3.3V : Min. LVPWELL Width. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.1_5V</name>
   <description>LPW.1_5V : Min. LVPWELL Width. : 0.74µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.2a_3.3V</name>
   <description>LPW.2a_3.3V : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.2a_5V</name>
   <description>LPW.2a_5V : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.2b_3.3V</name>
   <description>LPW.2b_3.3V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.2b_5V</name>
   <description>LPW.2b_5V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.3_3.3V</name>
   <description>LPW.3_3.3V : Min. DNWELL enclose LVPWELL. : 2.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.3_5V</name>
   <description>LPW.3_5V : Min. DNWELL enclose LVPWELL. : 2.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.5_3.3V</name>
   <description>LPW.5_3.3V : LVPWELL resistors must be enclosed by DNWELL.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.5_5V</name>
   <description>LPW.5_5V : LVPWELL resistors must be enclosed by DNWELL.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.11</name>
   <description>LPW.11 : Min. (LVPWELL outside DNWELL) space to DNWELL. : 1.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>LPW.12</name>
   <description>LPW.12 : LVPWELL cannot overlap with Nwell.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.1a_3.3V</name>
   <description>NW.1a_3.3V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.1a_5V</name>
   <description>NW.1a_5V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.1b_3.3V</name>
   <description>NW.1b_3.3V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.1b_5V</name>
   <description>NW.1b_5V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.2a_3.3V</name>
   <description>NW.2a_3.3V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.2a_5V</name>
   <description>NW.2a_5V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.2b_3.3V</name>
   <description>NW.2b_3.3V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.2b_5V</name>
   <description>NW.2b_5V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.3_3.3V</name>
   <description>NW.3_3.3V : Min. Nwell to DNWELL space. : 3.1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.3_5V</name>
   <description>NW.3_5V : Min. Nwell to DNWELL space. : 3.1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.4_3.3V</name>
   <description>NW.4_3.3V : Min. Nwell to LVPWELL space.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.4_5V</name>
   <description>NW.4_5V : Min. Nwell to LVPWELL space.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.5_3.3V</name>
   <description>NW.5_3.3V : Min. DNWELL enclose Nwell. : 0.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.5_5V</name>
   <description>NW.5_5V : Min. DNWELL enclose Nwell. : 0.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NW.6</name>
   <description>NW.6 : Nwell resistors can only exist outside DNWELL.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.1a_3.3V</name>
   <description>DF.1a_3.3V : Min. COMP Width. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.1a_5V</name>
   <description>DF.1a_5V : Min. COMP Width. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.1c_3.3V</name>
   <description>DF.1c_3.3V : Min. COMP Width for MOSCAP. : 1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.1c_5V</name>
   <description>DF.1c_5V : Min. COMP Width for MOSCAP. : 1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.2a_3.3V</name>
   <description>DF.2a_3.3V : Min Channel Width. : nil,0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.2a_5V</name>
   <description>DF.2a_5V : Min Channel Width. : nil,0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.2b_3.3V</name>
   <description>DF.2b_3.3V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.2b_5V</name>
   <description>DF.2b_5V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.3a_3.3V</name>
   <description>DF.3a_3.3V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.28µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.3a_5V</name>
   <description>DF.3a_5V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.36µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.3b_3.3V</name>
   <description>DF.3b_3.3V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.3b_5V</name>
   <description>DF.3b_5V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.3c_3.3V</name>
   <description>DF.3c_3.3V : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.3c_5V</name>
   <description>DF.3c_5V : Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4a_3.3V</name>
   <description>DF.4a_3.3V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4a_5V</name>
   <description>DF.4a_5V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4b_3.3V</name>
   <description>DF.4b_3.3V : Min. DNWELL overlap of NCOMP well tap. : 0.62µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4b_5V</name>
   <description>DF.4b_5V : Min. DNWELL overlap of NCOMP well tap. : 0.66µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4c_3.3V</name>
   <description>DF.4c_3.3V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.43µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4c_5V</name>
   <description>DF.4c_5V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4d_3.3V</name>
   <description>DF.4d_3.3V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.12µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4d_5V</name>
   <description>DF.4d_5V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4e_3.3V</name>
   <description>DF.4e_3.3V : Min. DNWELL overlap of PCOMP. : 0.93µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.4e_5V</name>
   <description>DF.4e_5V : Min. DNWELL overlap of PCOMP. : 1.1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.5_3.3V</name>
   <description>DF.5_3.3V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.12µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.5_5V</name>
   <description>DF.5_5V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.6_3.3V</name>
   <description>DF.6_3.3V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.6_5V</name>
   <description>DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.7_3.3V</name>
   <description>DF.7_3.3V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.7_5V</name>
   <description>DF.7_5V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.8_3.3V</name>
   <description>DF.8_3.3V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.43µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.8_5V</name>
   <description>DF.8_5V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.9_3.3V</name>
   <description>DF.9_3.3V : Min. COMP area (um2). : 0.2025µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.9_5V</name>
   <description>DF.9_5V : Min. COMP area (um2). : 0.2025µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.10_3.3V</name>
   <description>DF.10_3.3V : Min. field area (um2). : 0.26µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.10_5V</name>
   <description>DF.10_5V : Min. field area (um2). : 0.26µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.11_3.3V</name>
   <description>DF.11_3.3V : Min. Length of butting COMP edge. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.11_5V</name>
   <description>DF.11_5V : Min. Length of butting COMP edge. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.12_3.3V</name>
   <description>DF.12_3.3V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.12_5V</name>
   <description>DF.12_5V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.13_3.3V</name>
   <description>DF.13_3.3V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.13_5V</name>
   <description>DF.13_5V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.14_3.3V</name>
   <description>DF.14_3.3V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.14_5V</name>
   <description>DF.14_5V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.16_3.3V</name>
   <description>DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.16_5V</name>
   <description>DF.16_5V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.17_3.3V</name>
   <description>DF.17_3.3V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.17_5V</name>
   <description>DF.17_5V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.18_3.3V</name>
   <description>DF.18_3.3V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.18_5V</name>
   <description>DF.18_5V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.19_3.3V</name>
   <description>DF.19_3.3V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DF.19_5V</name>
   <description>DF.19_5V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.1</name>
   <description>DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.2</name>
   <description>DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.3</name>
   <description>DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.5</name>
   <description>DV.5 : Min. Dualgate width. : 0.7µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.6</name>
   <description>DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.7</name>
   <description>DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.8</name>
   <description>DV.8 : Min Dualgate enclose Poly2. : 0.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.9</name>
   <description>DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.1_3.3V</name>
   <description>PL.1_3.3V : Interconnect Width (outside PLFUSE). : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.1_5V</name>
   <description>PL.1_5V : Interconnect Width (outside PLFUSE). : 0.2µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.1a_3.3V</name>
   <description>PL.1a_3.3V : Interconnect Width (inside PLFUSE). : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.1a_5V</name>
   <description>PL.1a_5V : Interconnect Width (inside PLFUSE). : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.2_3.3V</name>
   <description>PL.2_3.3V : Gate Width (Channel Length). : 0.28µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.2_5V</name>
   <description>PL.2_5V : Gate Width (Channel Length).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.3a_3.3V</name>
   <description>PL.3a_3.3V : Space on COMP/Field. : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.3a_5V</name>
   <description>PL.3a_5V : Space on COMP/Field. : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.4_3.3V</name>
   <description>PL.4_3.3V : Extension beyond COMP to form Poly2 end cap. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.4_5V</name>
   <description>PL.4_5V : Extension beyond COMP to form Poly2 end cap. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.5a_3.3V</name>
   <description>PL.5a_3.3V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.5a_5V</name>
   <description>PL.5a_5V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.5b_3.3V</name>
   <description>PL.5b_3.3V : Space from field Poly2 to related COMP. : 0.1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.5b_5V</name>
   <description>PL.5b_5V : Space from field Poly2 to related COMP. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.6</name>
   <description>PL.6 : 90 degree bends on the COMP are not allowed.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.7_3.3V</name>
   <description>PL.7_3.3V : 45 degree bent gate width : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.7_5V</name>
   <description>PL.7_5V : 45 degree bent gate width : 0.7µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.9</name>
   <description>PL.9 : Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.11</name>
   <description>PL.11 : V5_Xtor must enclose 5V device.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PL.12</name>
   <description>PL.12 : V5_Xtor enclose 5V Comp.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.1</name>
   <description>NP.1 : min. nplus width : 0.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.2</name>
   <description>NP.2 : min. nplus spacing : 0.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.3a</name>
   <description>NP.3a : Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.3bi</name>
   <description>NP.3bi : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL &lt; 0.43um. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.3bii</name>
   <description>NP.3bii : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL &gt;= 0.43um. : 0.08µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.3ci</name>
   <description>NP.3ci : Space to PCOMP: For Outside DNWELL:(i) For PCOMP space to Nwell &lt; 0.43um. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.3cii</name>
   <description>NP.3cii : Space to PCOMP: For Outside DNWELL:(ii) For PCOMP space to Nwell &gt;= 0.43um. : 0.08µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.3d</name>
   <description>NP.3d : Min/max space to a butted PCOMP.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.3e</name>
   <description>NP.3e : Space to related PCOMP edge adjacent to a butting edge.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.4a</name>
   <description>NP.4a : Space to related P-channel gate at a butting edge parallel to gate. : 0.32µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.4b</name>
   <description>NP.4b : Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.5a</name>
   <description>NP.5a : Overlap of N-channel gate. : 0.23µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.5b</name>
   <description>NP.5b : Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.5ci</name>
   <description>NP.5ci : Extension beyond COMP: For Inside DNWELL: (i)For Nplus &lt; 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.5cii</name>
   <description>NP.5cii : Extension beyond COMP: For Inside DNWELL: (ii) For Nplus &gt;= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.02µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.5di</name>
   <description>NP.5di : Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus &lt; 0.43um. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.5dii</name>
   <description>NP.5dii : Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus &gt;= 0.43um. : 0.02µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.6</name>
   <description>NP.6 : Overlap with NCOMP butted to PCOMP. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.7</name>
   <description>NP.7 : Space to unrelated unsalicided Poly2. : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.8a</name>
   <description>NP.8a : Minimum Nplus area (um2). : 0.35µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.8b</name>
   <description>NP.8b : Minimum area enclosed by Nplus (um2). : 0.35µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.9</name>
   <description>NP.9 : Overlap of unsalicided Poly2. : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.10</name>
   <description>NP.10 : Overlap of unsalicided COMP. : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.11</name>
   <description>NP.11 : Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>NP.12</name>
   <description>NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.1</name>
   <description>PP.1 : min. pplus width : 0.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.2</name>
   <description>PP.2 : min. pplus spacing : 0.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.3a</name>
   <description>PP.3a : Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.3bi</name>
   <description>PP.3bi : Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL &gt;= 0.43um. : 0.08µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.3bii</name>
   <description>PP.3bii : Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL &lt; 0.43um. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.3ci</name>
   <description>PP.3ci : Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP &gt;= 0.43um. : 0.08µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.3cii</name>
   <description>PP.3cii : Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.3d</name>
   <description>PP.3d : Min/max space to a butted NCOMP.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.3e</name>
   <description>PP.3e : Space to NCOMP edge adjacent to a butting edge.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.4a</name>
   <description>PP.4a : Space related to N-channel gate at a butting edge parallel to gate. : 0.32µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.4b</name>
   <description>PP.4b : Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.5a</name>
   <description>PP.5a : Overlap of P-channel gate. : 0.23µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.5b</name>
   <description>PP.5b : Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.5ci</name>
   <description>PP.5ci : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus &gt;= 0.43um for LVPWELL tap. : 0.02µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.5cii</name>
   <description>PP.5cii : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus &lt; 0.43um for the LVPWELL tap. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.5di</name>
   <description>PP.5di : Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space &gt;= 0.43um for Pfield or LVPWELL tap. : 0.02µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.5dii</name>
   <description>PP.5dii : Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space &lt; 0.43um for Pfield or LVPWELL tap. : 0.16µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.6</name>
   <description>PP.6 : Overlap with PCOMP butted to NCOMP. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.7</name>
   <description>PP.7 : Space to unrelated unsalicided Poly2. : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.8a</name>
   <description>PP.8a : Minimum Pplus area (um2). : 0.35µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.8b</name>
   <description>PP.8b : Minimum area enclosed by Pplus (um2). : 0.35µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.9</name>
   <description>PP.9 : Overlap of unsalicided Poly2. : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.10</name>
   <description>PP.10 : Overlap of unsalicided COMP. : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.11</name>
   <description>PP.11 : Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>PP.12</name>
   <description>PP.12 : Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.1</name>
   <description>SB.1 : min. sab width : 0.42µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.2</name>
   <description>SB.2 : min. sab spacing : 0.42µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.3</name>
   <description>SB.3 : Space from salicide block to unrelated COMP. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.4</name>
   <description>SB.4 : Space from salicide block to contact.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.5a</name>
   <description>SB.5a : Space from salicide block to unrelated Poly2 on field. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.5b</name>
   <description>SB.5b : Space from salicide block to unrelated Poly2 on COMP. : 0.28µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.6</name>
   <description>SB.6 : Salicide block extension beyond related COMP. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.7</name>
   <description>SB.7 : COMP extension beyond related salicide block. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.8</name>
   <description>SB.8 : Non-salicided contacts are forbidden.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.9</name>
   <description>SB.9 : Salicide block extension beyond unsalicided Poly2. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.10</name>
   <description>SB.10 : Poly2 extension beyond related salicide block. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.11</name>
   <description>SB.11 : Overlap with COMP. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.12</name>
   <description>SB.12 : Overlap with Poly2 outside ESD_MK. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.13</name>
   <description>SB.13 : Min. area (um2). : 2µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.14a</name>
   <description>SB.14a : Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). : 0.56µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.14b</name>
   <description>SB.14b : Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). : 0.56µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.15a</name>
   <description>SB.15a : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.18µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.15b</name>
   <description>SB.15b : Space from unsalicided Poly2 to unrelated Nplus/Pplus along Poly2 line. : 0.32µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>SB.16</name>
   <description>SB.16 : SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.1</name>
   <description>ESD.1 : Minimum width of an ESD implant area. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.2</name>
   <description>ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.3a</name>
   <description>ESD.3a : Minimum space to NCOMP. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.3b</name>
   <description>ESD.3b : Min/max space to a butted PCOMP.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.4a</name>
   <description>ESD.4a : Extension beyond NCOMP. : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.4b</name>
   <description>ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.5a</name>
   <description>ESD.5a : Minimum ESD area (um2). : 0.49µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.5b</name>
   <description>ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.6</name>
   <description>ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.7</name>
   <description>ESD.7 : No ESD implant inside PCOMP.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.8</name>
   <description>ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.pl</name>
   <description>ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.9</name>
   <description>ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.10</name>
   <description>ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.1</name>
   <description>CO.1 : Min/max contact size. : 0.22µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.2a</name>
   <description>CO.2a : min. contact spacing : 0.25µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.2b</name>
   <description>CO.2b : Space in 4x4 or larger contact array. : 0.28µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.3</name>
   <description>CO.3 : Poly2 overlap of contact. : 0.07µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.4</name>
   <description>CO.4 : COMP overlap of contact. : 0.07µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.5a</name>
   <description>CO.5a : Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.5b</name>
   <description>CO.5b : Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.6</name>
   <description>CO.6 : Metal1 overlap of contact.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.6a</name>
   <description>CO.6a : (i) Metal1 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.6b</name>
   <description>CO.6b : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap : 0.06µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.7</name>
   <description>CO.7 : Space from COMP contact to Poly2 on COMP. : 0.15µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.8</name>
   <description>CO.8 : Space from Poly2 contact to COMP. : 0.17µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.9</name>
   <description>CO.9 : Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.10</name>
   <description>CO.10 : Contact on Poly2 gate over COMP is forbidden.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>CO.11</name>
   <description>CO.11 : Contact on field oxide is forbidden.</description>
   <categories>
   </categories>
  </category>
 </categories>
 <cells>
  <cell>
   <name>user_project_wrapper</name>
   <variant/>
   <references>
   </references>
  </cell>
 </cells>
 <items>
 </items>
</report-database>