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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-012 / 655d91999f45d3a98393176a7c338a3b1d73a94e / . / mpw_precheck / outputs / reports / klayout_beol_check.xml
blob: 692690d32a0909381cc1e41a64ce0d984d7d8013 [file] [log] [blame]
<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>DRC Run Report at</description>
<original-file/>
<generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
<top-cell>user_project_wrapper</top-cell>
<tags>
</tags>
<categories>
<category>
<name>M1.1</name>
<description>M1.1 : min. metal1 width : 0.23µm</description>
<categories>
</categories>
</category>
<category>
<name>M1.2a</name>
<description>M1.2a : min. metal1 spacing : 0.23µm</description>
<categories>
</categories>
</category>
<category>
<name>M1.2b</name>
<description>M1.2b : Space to wide Metal1 (length &amp; width &gt; 10um) : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>M1.3</name>
<description>M1.3 : Minimum Metal1 area : 0.1444µm²</description>
<categories>
</categories>
</category>
<category>
<name>M2.1</name>
<description>M2.1 : min. metal2 width : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M2.2a</name>
<description>M2.2a : min. metal2 spacing : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M2.2b</name>
<description>M2.2b : Space to wide Metal2 (length &amp; width &gt; 10um) : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>M2.3</name>
<description>M2.3 : Minimum metal2 area : 0.1444µm²</description>
<categories>
</categories>
</category>
<category>
<name>M3.1</name>
<description>M3.1 : min. metal3 width : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M3.2a</name>
<description>M3.2a : min. metal3 spacing : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M3.2b</name>
<description>M3.2b : Space to wide Metal3 (length &amp; width &gt; 10um) : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>M3.3</name>
<description>M3.3 : Minimum metal3 area : 0.1444µm²</description>
<categories>
</categories>
</category>
<category>
<name>M4.1</name>
<description>M4.1 : min. metal4 width : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M4.2a</name>
<description>M4.2a : min. metal4 spacing : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M4.2b</name>
<description>M4.2b : Space to wide Metal4 (length &amp; width &gt; 10um) : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>M4.3</name>
<description>M4.3 : Minimum metal4 area : 0.1444µm²</description>
<categories>
</categories>
</category>
<category>
<name>M5.1</name>
<description>M5.1 : min. metal5 width : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M5.2a</name>
<description>M5.2a : min. metal5 spacing : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>M5.2b</name>
<description>M5.2b : Space to wide Metal5 (length &amp; width &gt; 10um) : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>M5.3</name>
<description>M5.3 : Minimum metal5 area : 0.1444µm²</description>
<categories>
</categories>
</category>
<category>
<name>V1.1</name>
<description>V1.1 : Min/max Via1 size . : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V1.2a</name>
<description>V1.2a : min. via1 spacing : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V1.2b</name>
<description>V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm</description>
<categories>
</categories>
</category>
<category>
<name>V1.3a</name>
<description>V1.3a : metal-1 overlap of via1.</description>
<categories>
</categories>
</category>
<category>
<name>V1.3c</name>
<description>V1.3c : metal-1 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V1.3d</name>
<description>V1.3d : If metal-1 overlap via1 by &lt; 0.04um on one side, adjacent metal-1 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V1.4a</name>
<description>V1.4a : metal-2 overlap of via1.</description>
<categories>
</categories>
</category>
<category>
<name>V1.4b</name>
<description>V1.4b : metal-2 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V1.4c</name>
<description>V1.4c : If metal-2 overlap via1 by &lt; 0.04um on one side, adjacent metal-2 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V2.1</name>
<description>V2.1 : Min/max Via2 size . : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V2.2a</name>
<description>V2.2a : min. via2 spacing : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V2.2b</name>
<description>V2.2b : Via2 Space in 4x4 or larger via2 array : 0.36µm</description>
<categories>
</categories>
</category>
<category>
<name>V2.3b</name>
<description>V2.3b : metal2 overlap of via2.</description>
<categories>
</categories>
</category>
<category>
<name>V2.3c</name>
<description>V2.3c : metal2 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V2.3d</name>
<description>V2.3d : If metal2 overlap via2 by &lt; 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V2.4a</name>
<description>V2.4a : metal3 overlap of via2.</description>
<categories>
</categories>
</category>
<category>
<name>V2.4b</name>
<description>V2.4b : metal3 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V2.4c</name>
<description>V2.4c : If metal3 overlap via2 by &lt; 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V3.1</name>
<description>V3.1 : Min/max Via3 size . : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V3.2a</name>
<description>V3.2a : min. via3 spacing : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V3.2b</name>
<description>V3.2b : Via3 Space in 4x4 or larger via3 array : 0.36µm</description>
<categories>
</categories>
</category>
<category>
<name>V3.3b</name>
<description>V3.3b : metal3 overlap of via3.</description>
<categories>
</categories>
</category>
<category>
<name>V3.3c</name>
<description>V3.3c : metal3 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V3.3d</name>
<description>V3.3d : If metal3 overlap via3 by &lt; 0.04um on one side, adjacent metal3 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V3.4a</name>
<description>V3.4a : metal4 overlap of via3.</description>
<categories>
</categories>
</category>
<category>
<name>V3.4b</name>
<description>V3.4b : metal4 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V3.4c</name>
<description>V3.4c : If metal4 overlap via3 by &lt; 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V4.1</name>
<description>V4.1 : Min/max Via4 size . : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V4.2a</name>
<description>V4.2a : min. via4 spacing : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V4.2b</name>
<description>V4.2b : Via4 Space in 4x4 or larger Vian array : 0.36µm</description>
<categories>
</categories>
</category>
<category>
<name>V4.3b</name>
<description>V4.3b : metal4 overlap of via4.</description>
<categories>
</categories>
</category>
<category>
<name>V4.3c</name>
<description>V4.3c : metal4 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V4.3d</name>
<description>V4.3d : If metal4 overlap Vian by &lt; 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V4.4a</name>
<description>V4.4a : metal5 overlap of via4.</description>
<categories>
</categories>
</category>
<category>
<name>V4.4b</name>
<description>V4.4b : metal5 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V4.4c</name>
<description>V4.4c : If metal5 overlap via4 by &lt; 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V5.1</name>
<description>V5.1 : Min/max Via5 size . : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V5.2a</name>
<description>V5.2a : min. via5 spacing : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>V5.2b</name>
<description>V5.2b : Via5 Space in 4x4 or larger via5 array : 0.36µm</description>
<categories>
</categories>
</category>
<category>
<name>V5.3b</name>
<description>V5.3b : metal5 overlap of via5.</description>
<categories>
</categories>
</category>
<category>
<name>V5.3c</name>
<description>V5.3c : metal5 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V5.3d</name>
<description>V5.3d : If metal5 overlap via5 by &lt; 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V5.4a</name>
<description>V5.4a : metaltop overlap of via5.</description>
<categories>
</categories>
</category>
<category>
<name>V5.4b</name>
<description>V5.4b : metaltop (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>V5.4c</name>
<description>V5.4c : If metaltop overlap via5 by &lt; 0.04um on one side, adjacent metaltop edges overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>MT.1</name>
<description>MT.1 : min. metaltop width : 0.44µm</description>
<categories>
</categories>
</category>
<category>
<name>MT.2a</name>
<description>MT.2a : min. metaltop spacing : 0.46µm</description>
<categories>
</categories>
</category>
<category>
<name>MT.4</name>
<description>MT.4 : Minimum MetalTop area : 0.5625µm²</description>
<categories>
</categories>
</category>
<category>
<name>MC.1</name>
<description>MC.1 : min. mcell width : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MC.2</name>
<description>MC.2 : min. mcell spacing : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MC.3</name>
<description>MC.3 : Minimum Mcell area : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>MC.4</name>
<description>MC.4 : Minimum area enclosed by Mcell : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>PRES.1</name>
<description>PRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.2</name>
<description>PRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.3</name>
<description>PRES.3 : Minimum space from Poly2 resistor to COMP.</description>
<categories>
</categories>
</category>
<category>
<name>PRES.4</name>
<description>PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.5</name>
<description>PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.6</name>
<description>PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.7</name>
<description>PRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
<categories>
</categories>
</category>
<category>
<name>PRES.9a</name>
<description>PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.</description>
<categories>
</categories>
</category>
<category>
<name>PRES.9b</name>
<description>PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.1</name>
<description>LRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.2</name>
<description>LRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.3</name>
<description>LRES.3 : Minimum space from Poly2 resistor to COMP.</description>
<categories>
</categories>
</category>
<category>
<name>LRES.4</name>
<description>LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.5</name>
<description>LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.6</name>
<description>LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.7</name>
<description>LRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
<categories>
</categories>
</category>
<category>
<name>LRES.9a</name>
<description>LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. </description>
<categories>
</categories>
</category>
<category>
<name>LRES.9b</name>
<description>LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.1</name>
<description>HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.2</name>
<description>HRES.2 : Minimum width of Poly2 resistor. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.3</name>
<description>HRES.3 : Minimum space between Poly2 resistors. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.4</name>
<description>HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.5</name>
<description>HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.6</name>
<description>HRES.6 : Minimum RESISTOR space to COMP.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.7</name>
<description>HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.8</name>
<description>HRES.8 : Space from salicide block to contact on Poly2 resistor.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.9</name>
<description>HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.10</name>
<description>HRES.10 : Minimum &amp; maximum Pplus overlap of SAB.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.12a</name>
<description>HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. </description>
<categories>
</categories>
</category>
<category>
<name>HRES.12b</name>
<description>HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.1</name>
<description>MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.2</name>
<description>MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.3</name>
<description>MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.4</name>
<description>MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.5</name>
<description>MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.6</name>
<description>MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.7</name>
<description>MIMTM.7 : Min FuseTop enclosure by CAP_MK.</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.8a</name>
<description>MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.8b</name>
<description>MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.9</name>
<description>MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.10</name>
<description>MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.11</name>
<description>MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.1</name>
<description>NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.2</name>
<description>NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.3</name>
<description>NAT.3 : Space to NWell edge. : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.4</name>
<description>NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.5</name>
<description>NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.6</name>
<description>NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.7</name>
<description>NAT.7 : Minimum NAT to NAT spacing. : 0.74µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.8</name>
<description>NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.9</name>
<description>NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.10</name>
<description>NAT.10 : Nwell, inside NAT layer are not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.11</name>
<description>NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.12</name>
<description>NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).</description>
<categories>
</categories>
</category>
<category>
<name>BJT.1</name>
<description>BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.</description>
<categories>
</categories>
</category>
<category>
<name>BJT.2</name>
<description>BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.</description>
<categories>
</categories>
</category>
<category>
<name>BJT.3</name>
<description>BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>DE.2</name>
<description>DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm</description>
<categories>
</categories>
</category>
<category>
<name>DE.3</name>
<description>DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).</description>
<categories>
</categories>
</category>
<category>
<name>DE.4</name>
<description>DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>LVS_BJT.1</name>
<description>LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers</description>
<categories>
</categories>
</category>
<category>
<name>O.DF.3a</name>
<description>O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>O.DF.6</name>
<description>O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>O.DF.9</name>
<description>O.DF.9 : Min. COMP area (um2). : 0.1444µm²</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.2</name>
<description>O.PL.2 : Min. poly2 width. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.3a</name>
<description>O.PL.3a : Min. poly2 Space on COMP. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.4</name>
<description>O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.2</name>
<description>O.SB.2 : Min. salicide Block Space. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.3</name>
<description>O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.4</name>
<description>O.SB.4 : Min. space from salicide block to contact.</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.5b_3.3V</name>
<description>O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.9</name>
<description>O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.11</name>
<description>O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.13_3.3V</name>
<description>O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.13_5V</name>
<description>O.SB.13_5V : Min. area of silicide block (um2). : 2µm²</description>
<categories>
</categories>
</category>
<category>
<name>O.CO.7</name>
<description>O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.ORT</name>
<description>O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.01</name>
<description>EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.</description>
<categories>
</categories>
</category>
<category>
<name>EF.02</name>
<description>EF.02 : Min. Max. PLFUSE width. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.03</name>
<description>EF.03 : Min. Max. PLFUSE length. : 1.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.04a</name>
<description>EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.</description>
<categories>
</categories>
</category>
<category>
<name>EF.04b</name>
<description>EF.04b : PLFUSE must be rectangular. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.04c</name>
<description>EF.04c : Cathode Poly2 must be rectangular. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.04d</name>
<description>EF.04d : Anode Poly2 must be rectangular. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.05</name>
<description>EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).</description>
<categories>
</categories>
</category>
<category>
<name>EF.06</name>
<description>EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.07</name>
<description>EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.08</name>
<description>EF.08 : Min./Max. Anode Poly2 width. : 1.06µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.09</name>
<description>EF.09 : Min./Max. Anode Poly2 length. : 2.43µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.10</name>
<description>EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.11</name>
<description>EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.12</name>
<description>EF.12 : Min. Space of Cathode Contact to PLFUSE end.</description>
<categories>
</categories>
</category>
<category>
<name>EF.13</name>
<description>EF.13 : Min. Space of Anode Contact to PLFUSE end.</description>
<categories>
</categories>
</category>
<category>
<name>EF.14</name>
<description>EF.14 : Min. EFUSE_MK enclose LVS_Source.</description>
<categories>
</categories>
</category>
<category>
<name>EF.15</name>
<description>EF.15 : NO Contact is allowed to touch PLFUSE.</description>
<categories>
</categories>
</category>
<category>
<name>EF.16a</name>
<description>EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.16b</name>
<description>EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.17</name>
<description>EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.18</name>
<description>EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.</description>
<categories>
</categories>
</category>
<category>
<name>EF.19</name>
<description>EF.19 : Min. PLFUSE space to Metal1, Metal2.</description>
<categories>
</categories>
</category>
<category>
<name>EF.20</name>
<description>EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.21</name>
<description>EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.22a</name>
<description>EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.22b</name>
<description>EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.1</name>
<description>MDN.1 : Min MVSD width (for litho purpose). : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.2a</name>
<description>MDN.2a : Min MVSD space [Same Potential]. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.2b</name>
<description>MDN.2b : Min MVSD space [Diff Potential]. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.3a</name>
<description>MDN.3a : Min transistor channel length. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.3b</name>
<description>MDN.3b : Max transistor channel length.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.4a</name>
<description>MDN.4a : Min transistor channel width. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.4b</name>
<description>MDN.4b : Max transistor channel width.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.5ai</name>
<description>MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.5aii</name>
<description>MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.5b</name>
<description>MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.5c</name>
<description>MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.6</name>
<description>MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.6a</name>
<description>MDN.6a : Min Dualgate enclose NCOMP.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.7</name>
<description>MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.7a</name>
<description>MDN.7a : Min LDMOS_XTOR enclose Dualgate.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.8a</name>
<description>MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.8b</name>
<description>MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.9</name>
<description>MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10a</name>
<description>MDN.10a : Min LDNMOS POLY2 width. : 1.2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10b</name>
<description>MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10c</name>
<description>MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10d</name>
<description>MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10ei</name>
<description>MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10eii</name>
<description>MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10f</name>
<description>MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.11</name>
<description>MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).</description>
<categories>
</categories>
</category>
<category>
<name>MDN.12</name>
<description>MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13a</name>
<description>MDN.13a : Max single finger width. : 50µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13b</name>
<description>MDN.13b : Layout shall have alternative source &amp; drain.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13c</name>
<description>MDN.13c : Both sides of the transistor shall be terminated by source.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13d</name>
<description>MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).</description>
<categories>
</categories>
</category>
<category>
<name>MDN.14</name>
<description>MDN.14 : Min MVSD space to any DNWELL.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.15a</name>
<description>MDN.15a : Min LDNMOS drain COMP width. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.15b</name>
<description>MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.17</name>
<description>MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.1</name>
<description>MDP.1 : Minimum transistor channel length. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.1a</name>
<description>MDP.1a : Max transistor channel length.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.2</name>
<description>MDP.2 : Minimum transistor channel width. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3</name>
<description>MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3ai</name>
<description>MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3aii</name>
<description>MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3b</name>
<description>MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3c</name>
<description>MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3d</name>
<description>MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.4</name>
<description>MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.4a</name>
<description>MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.4b</name>
<description>MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.5</name>
<description>MDP.5 : Each LDPMOS shall be covered by Dualgate layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.5a</name>
<description>MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.6</name>
<description>MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.6a</name>
<description>MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.7</name>
<description>MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.8</name>
<description>MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9a</name>
<description>MDP.9a : Min LDPMOS POLY2 width. : 1.2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9b</name>
<description>MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9c</name>
<description>MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9d</name>
<description>MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9ei</name>
<description>MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9eii</name>
<description>MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9f</name>
<description>MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.10</name>
<description>MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).</description>
<categories>
</categories>
</category>
<category>
<name>MDP.10a</name>
<description>MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.10b</name>
<description>MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.11</name>
<description>MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.12</name>
<description>MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.13a</name>
<description>MDP.13a : Max single finger width. : 50µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.13b</name>
<description>MDP.13b : Layout shall have alternative source &amp; drain.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.13c</name>
<description>MDP.13c : Both sides of the transistor shall be terminated by source.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.15</name>
<description>MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.16a</name>
<description>MDP.16a : Min LDPMOS drain COMP width. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.16b</name>
<description>MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.17a</name>
<description>MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.17c</name>
<description>MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential</description>
<categories>
</categories>
</category>
<category>
<name>Y.NW.2b_3.3V</name>
<description>Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.NW.2b_5V</name>
<description>Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.DF.6_5V</name>
<description>Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.DF.16_3.3V</name>
<description>Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.DF.16_5V</name>
<description>Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.1_3.3V</name>
<description>Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.1_5V</name>
<description>Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.2_3.3V</name>
<description>Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.2_5V</name>
<description>Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.4_5V</name>
<description>Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5a_3.3V</name>
<description>Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5a_5V</name>
<description>Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5b_3.3V</name>
<description>Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5b_5V</name>
<description>Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.4c_MV</name>
<description>S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.6_MV</name>
<description>S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.7_MV</name>
<description>S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.8_MV</name>
<description>S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.16_MV</name>
<description>S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.PL.5a_MV</name>
<description>S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>S.PL.5b_MV</name>
<description>S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.4_MV</name>
<description>S.CO.4_MV : COMP overlap of contact. : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.4c_LV</name>
<description>S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.16_LV</name>
<description>S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.3_LV</name>
<description>S.CO.3_LV : Poly2 overlap of contact. : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.4_LV</name>
<description>S.CO.4_LV : COMP overlap of contact. : 0.03µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.6_ii_LV</name>
<description>S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap</description>
<categories>
</categories>
</category>
<category>
<name>S.M1.1_LV</name>
<description>S.M1.1_LV : min. metal1 width : 0.22µm</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>user_project_wrapper</name>
<variant/>
<references>
</references>
</cell>
</cells>
<items>
</items>
</report-database>