verilog: fix module name
2 files changed
tree: 65e01257250b59d5b19e401ea7075bbf3dd0e547
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Tiny User Project

Template for submitting TinyTapeout based projects to the Open MPW shuttle program.

Usage

  1. Generate a new project based on this template

  2. Create a new Wokwi project and update WOKWI_PROJECT_ID.

  3. Push and check the user_project_ci workflow summary (if successful a new commit including the hardened files will be automatically created).

  4. Submit your project github repository to the next Open MPW shuttle.