verilog: fix module name

verilog/rtl/tiny_user_project.v

diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
index e883560..cfea228 100644
--- a/verilog/rtl/tiny_user_project.v
+++ b/verilog/rtl/tiny_user_project.v
@@ -21,7 +21,7 @@
 );
 
 // pass input and output pins defined in user_defines.v
-user_module module (
+user_module mod (
     .io_in (io_in[19:12]),
     .io_out(io_out[27:20])
 );
@@ -29,4 +29,5 @@
 assign io_oeb[27:20] = 8'b0;
 
 endmodule	// tiny_user_project
+
 `default_nettype wire
\ No newline at end of file

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9fdd268..e0abba8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -89,4 +89,5 @@
 );
 
 endmodule	// user_project_wrapper
+
 `default_nettype wire