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foss-eda-tools/third_party/shuttle/gf180mcu/mpw-000/slot-012/450d451ef45bd3dd9569cf9f9ea8485f1dc622e8^!/.
commit
450d451ef45bd3dd9569cf9f9ea8485f1dc622e8
[log]
author
Johan Euphrosine <proppy@google.com>
Sun Nov 13 00:45:14 2022 +0900
committer
Johan Euphrosine <proppy@google.com>
Sun Nov 13 00:56:18 2022 +0900
tree
5369cdddac66d4da83f8edf26da7baf87de18636
parent
9e8e8f7f00d400cc4cf4283a4749683ad344e0f3 [diff]
rename user project module

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 388070c..08cd177 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json

@@ -6,9 +6,9 @@
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
     "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
-    "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
-    "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
-    "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+    "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_module.v"],
+    "EXTRA_LEFS": "dir::../../lef/user_module.lef",
+    "EXTRA_GDS_FILES": "dir::../../gds/user_module.gds",
     "FP_PDN_CHECK_NODES": 0,
     "SYNTH_ELABORATE_ONLY": 1,
     "PL_RANDOM_GLB_PLACEMENT": 1,
@@ -82,4 +82,4 @@
         "MAGIC_WRITE_FULL_LEF": 0,
         "FP_PDN_ENABLE_RAILS": 0
    }
-}
\ No newline at end of file
+}

diff --git a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
index 7bf40c0..ac951d4 100644
--- a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def

@@ -1309,7 +1309,7 @@
     - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 350 400 350  + ROWCOL 2 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
+    - mprj user_module + FIXED ( 1175000 1690000 ) N ;
 END COMPONENTS
 PINS 645 ;
     - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL

diff --git a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
index 405d3ff..8ce3481 100644
--- a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def

@@ -778,7 +778,7 @@
     - via4_5_3200_6200_6_3_1040_1040 + VIARULE Via4_GEN_HH + CUTSIZE 520 520  + LAYERS Metal4 Via4 Metal5  + CUTSPACING 520 520  + ENCLOSURE 300 240 120 240  + ROWCOL 6 3  ;
 END VIAS
 COMPONENTS 1 ;
-    - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
+    - mprj user_module + FIXED ( 1175000 1690000 ) N ;
 END COMPONENTS
 PINS 645 ;
     - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL

diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
index 0ccc511..f052b54 100644
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ b/verilog/dv/io_ports/io_ports_tb.v

@@ -47,7 +47,7 @@
 
 	`ifdef ENABLE_SDF
 		initial begin
-			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
+			$sdf_annotate("../../../sdf/user_module.sdf", uut.mprj) ;
 			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;

diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index 6aeceb1..f433305 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v

@@ -40,7 +40,7 @@
 
 	`ifdef ENABLE_SDF
 		initial begin
-			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
+			$sdf_annotate("../../../sdf/user_module.sdf", uut.mprj) ;
 			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;

diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v
index fff3b72..6551972 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test2/la_test2_tb.v

@@ -40,7 +40,7 @@
 
 	`ifdef ENABLE_SDF
 		initial begin
-			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
+			$sdf_annotate("../../../sdf/user_module.sdf", uut.mprj) ;
 			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
 			// these breaks the simulation

diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index e44d5a2..37c01a6 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v

@@ -42,7 +42,7 @@
 
     `ifdef ENABLE_SDF
 		initial begin
-			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj.mprj) ;
+			$sdf_annotate("../../../sdf/user_module.sdf", uut.mprj.mprj) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
 			$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;

diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 26ff469..c3dee89 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v

@@ -45,7 +45,7 @@
 
 	`ifdef ENABLE_SDF
 		initial begin
-			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
+			$sdf_annotate("../../../sdf/user_module.sdf", uut.mprj) ;
 			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
 			$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;

diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
index 284a97c..d68969d 100644
--- a/verilog/includes/includes.gl+sdf.caravel_user_project
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project

@@ -1,3 +1,3 @@
 // Caravel user project includes		
 $USER_PROJECT_VERILOG/gl/user_project_wrapper.v	     
-$USER_PROJECT_VERILOG/gl/user_proj_example.v
+$USER_PROJECT_VERILOG/gl/user_module.v

diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index f5047d5..0bbcd8d 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project

@@ -1,3 +1,3 @@
 # Caravel user project includes	     
 -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v     
+-v $(USER_PROJECT_VERILOG)/gl/user_module.v     

diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..898b5cb 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project

@@ -1,5 +1,5 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/user_module.v
 
  
\ No newline at end of file

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..878a377 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v

@@ -21,8 +21,8 @@
     // Assume default net type to be wire because GL netlists don't have the wire definitions
     `default_nettype wire
     `include "gl/user_project_wrapper.v"
-    `include "gl/user_proj_example.v"
+    `include "gl/user_module.v"
 `else
     `include "user_project_wrapper.v"
-    `include "user_proj_example.v"
-`endif
\ No newline at end of file
+    `include "user_module.v"
+`endif