user_projext_wrapper: fix input pins range

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8f5eeab..2718539 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -83,7 +83,7 @@
 /*--------------------------------------*/
 
 user_module mprj (
-    .io_in (io_in[20:12]),
+    .io_in (io_in[19:12]),
     .io_out(io_out[27:20]),
 );