sdc/spell.sdc

###############################################################################
# Created by write_sdc
# Sat Dec  3 22:04:43 2022
###############################################################################
current_design spell
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clock -period 100.0000 [get_ports {clock}]
set_clock_transition 0.1500 [get_clocks {clock}]
set_clock_uncertainty 0.2500 clock
set_propagated_clock [get_clocks {clock}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_addr[0]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_addr[1]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_addr[2]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_addr[3]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_addr[4]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_addr[5]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_addr[6]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[0]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[1]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[2]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[3]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[4]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[5]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[6]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_data[7]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_wb_disable}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_la_write}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[0]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[10]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[11]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[12]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[13]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[14]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[15]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[16]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[17]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[18]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[19]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[1]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[20]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[21]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[22]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[23]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[24]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[25]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[26]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[27]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[28]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[29]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[2]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[30]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[31]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[3]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[4]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[5]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[6]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[7]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[8]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_addr[9]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_cyc}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[0]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[10]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[11]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[12]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[13]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[14]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[15]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[16]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[17]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[18]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[19]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[1]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[20]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[21]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[22]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[23]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[24]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[25]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[26]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[27]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[28]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[29]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[2]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[30]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[31]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[3]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[4]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[5]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[6]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[7]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[8]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_data[9]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_stb}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {i_wb_we}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[0]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[1]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[2]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[3]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[4]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[5]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[6]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_in[7]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_ack_i}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[0]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[10]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[11]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[12]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[13]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[14]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[15]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[16]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[17]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[18]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[19]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[1]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[20]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[21]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[22]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[23]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[24]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[25]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[26]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[27]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[28]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[29]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[2]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[30]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[31]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[3]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[4]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[5]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[6]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[7]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[8]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_i[9]}]
set_input_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {reset}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {interrupt}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[0]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[1]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[2]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[3]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[4]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[5]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[6]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_oeb[7]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[0]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[1]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[2]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[3]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[4]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[5]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[6]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_out[7]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[0]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[10]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[11]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[12]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[13]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[14]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[15]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[16]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[17]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[18]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[19]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[1]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[20]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[21]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[22]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[23]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[24]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[25]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[26]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[27]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[28]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[29]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[2]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[30]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[31]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[3]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[4]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[5]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[6]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[7]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[8]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {la_data_out[9]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_ack}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[0]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[10]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[11]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[12]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[13]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[14]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[15]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[16]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[17]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[18]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[19]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[1]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[20]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[21]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[22]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[23]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[24]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[25]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[26]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[27]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[28]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[29]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[2]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[30]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[31]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[3]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[4]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[5]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[6]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[7]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[8]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {o_wb_data[9]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[0]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[1]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[2]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[3]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[4]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[5]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[6]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[7]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[8]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_addr_o[9]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_clk_o}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_cyc_o}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[0]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[10]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[11]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[12]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[13]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[14]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[15]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[16]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[17]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[18]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[19]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[1]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[20]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[21]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[22]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[23]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[24]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[25]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[26]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[27]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[28]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[29]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[2]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[30]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[31]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[3]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[4]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[5]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[6]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[7]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[8]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_dat_o[9]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_rst_o}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_sel_o[0]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_sel_o[1]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_sel_o[2]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_sel_o[3]}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_stb_o}]
set_output_delay 20.0000 -clock [get_clocks {clock}] -add_delay [get_ports {rambus_wb_we_o}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0729 [get_ports {interrupt}]
set_load -pin_load 0.0729 [get_ports {o_wb_ack}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_clk_o}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_cyc_o}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_rst_o}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_stb_o}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_we_o}]
set_load -pin_load 0.0729 [get_ports {io_oeb[7]}]
set_load -pin_load 0.0729 [get_ports {io_oeb[6]}]
set_load -pin_load 0.0729 [get_ports {io_oeb[5]}]
set_load -pin_load 0.0729 [get_ports {io_oeb[4]}]
set_load -pin_load 0.0729 [get_ports {io_oeb[3]}]
set_load -pin_load 0.0729 [get_ports {io_oeb[2]}]
set_load -pin_load 0.0729 [get_ports {io_oeb[1]}]
set_load -pin_load 0.0729 [get_ports {io_oeb[0]}]
set_load -pin_load 0.0729 [get_ports {io_out[7]}]
set_load -pin_load 0.0729 [get_ports {io_out[6]}]
set_load -pin_load 0.0729 [get_ports {io_out[5]}]
set_load -pin_load 0.0729 [get_ports {io_out[4]}]
set_load -pin_load 0.0729 [get_ports {io_out[3]}]
set_load -pin_load 0.0729 [get_ports {io_out[2]}]
set_load -pin_load 0.0729 [get_ports {io_out[1]}]
set_load -pin_load 0.0729 [get_ports {io_out[0]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[31]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[30]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[29]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[28]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[27]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[26]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[25]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[24]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[23]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[22]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[21]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[20]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[19]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[18]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[17]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[16]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[15]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[14]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[13]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[12]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[11]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[10]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[9]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[8]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[7]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[6]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[5]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[4]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[3]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[2]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[1]}]
set_load -pin_load 0.0729 [get_ports {la_data_out[0]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[31]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[30]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[29]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[28]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[27]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[26]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[25]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[24]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[23]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[22]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[21]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[20]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[19]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[18]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[17]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[16]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[15]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[14]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[13]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[12]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[11]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[10]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[9]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[8]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[7]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[6]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[5]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[4]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[3]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[2]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[1]}]
set_load -pin_load 0.0729 [get_ports {o_wb_data[0]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[9]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[8]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[7]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[6]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[5]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[4]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[3]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[2]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[1]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_addr_o[0]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[31]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[30]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[29]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[28]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[27]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[26]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[25]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[24]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[23]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[22]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[21]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[20]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[19]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[18]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[17]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[16]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[15]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[14]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[13]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[12]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[11]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[10]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[9]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[8]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[7]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[6]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[5]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[4]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[3]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[2]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[1]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_dat_o[0]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_sel_o[3]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_sel_o[2]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_sel_o[1]}]
set_load -pin_load 0.0729 [get_ports {rambus_wb_sel_o[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_4 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clock}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_wb_disable}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_write}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_cyc}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_stb}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_we}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_ack_i}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_addr[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_addr[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_addr[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_addr[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_addr[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_addr[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_addr[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[7]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_la_data[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[31]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[30]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[29]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[28]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[27]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[26]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[25]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[24]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[23]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[22]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[21]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[20]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[19]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[18]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[17]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[16]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[15]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[14]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[13]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[12]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[11]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[10]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[9]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[8]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[7]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_addr[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[31]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[30]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[29]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[28]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[27]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[26]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[25]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[24]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[23]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[22]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[21]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[20]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[19]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[18]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[17]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[16]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[15]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[14]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[13]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[12]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[11]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[10]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[9]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[8]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[7]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i_wb_data[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[31]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[30]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[29]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[28]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[27]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[26]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[25]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[24]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[23]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[22]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[21]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[20]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[19]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[18]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[17]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[16]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[15]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[14]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[13]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[12]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[11]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[10]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[9]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[8]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[7]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[6]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[5]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[4]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[3]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[2]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[1]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 4.0000 [current_design]