| commit | c9d82251618bf23c2bad1c74a8e9b8b48e0e121a | [log] [tgz] |
|---|---|---|
| author | Matt Venn <matt@mattvenn.net> | Tue Nov 29 15:53:24 2022 +0100 |
| committer | Uri Shaked <uri@urishaked.com> | Sun Dec 04 00:00:10 2022 +0200 |
| tree | f737169146a7b0f2698cd77faa0d115008a620b3 | |
| parent | bc6a1129da94f23002e649708b1bacaba124708c [diff] |
add clock and reset, comment out ram_bus
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 2e78446..e3908ba 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -93,8 +93,10 @@ .o_wb_data(wbs_dat_o), // RAMBus ports - unused - .rambus_wb_ack_i (0), - .rambus_wb_dat_i (0), +// .rambus_wb_ack_i (0), + // .rambus_wb_dat_i (0), + .reset(wb_rst_i), + .clock(wb_clk_i), // IO pins .io_in(io_in[15:8]),