diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2e78446..e3908ba 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -93,8 +93,10 @@
     .o_wb_data(wbs_dat_o),
 
     // RAMBus ports - unused
-    .rambus_wb_ack_i   (0),
-    .rambus_wb_dat_i   (0),
+//    .rambus_wb_ack_i   (0),
+ //   .rambus_wb_dat_i   (0),
+    .reset(wb_rst_i),
+    .clock(wb_clk_i),
 
     // IO pins
     .io_in(io_in[15:8]),