| commit | f2b31f944184b2dc736c41cd9534932b60bfaa4b | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com> | Thu Oct 27 23:57:33 2022 -0700 |
| committer | GitHub <noreply@github.com> | Thu Oct 27 23:57:33 2022 -0700 |
| tree | d77dd8c96849f7294cfa4a0bc2bf37d996903df2 | |
| parent | fb0bd7f8c3599ff97a506ba72ade715ead407828 [diff] |
Update wb_port.c add def for reg_mprj_slave
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index e649f7c..c9c6996 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -19,6 +19,8 @@ #include <defs.h> #include <stub.c> +#define reg_mprj_slave (*(volatile uint32_t*)0x30000000) + /* Wishbone Test: - Configures MPRJ lower 8-IO pins as outputs