feat: add skullfet inverter
it doesn't harden yet, as user_project_wrapper fails with an LVS error
diff --git a/gds/skullfet_inverter.gds b/gds/skullfet_inverter.gds
new file mode 100755
index 0000000..7e953d7
--- /dev/null
+++ b/gds/skullfet_inverter.gds
Binary files differ
diff --git a/gds/skullfet_nand.gds b/gds/skullfet_nand.gds
new file mode 100755
index 0000000..bd07328
--- /dev/null
+++ b/gds/skullfet_nand.gds
Binary files differ
diff --git a/lef/skullfet_inverter.lef b/lef/skullfet_inverter.lef
new file mode 100755
index 0000000..db823fc
--- /dev/null
+++ b/lef/skullfet_inverter.lef
@@ -0,0 +1,135 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO skullfet_inverter
+ CLASS BLOCK ;
+ FOREIGN skullfet_inverter ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 53.500 BY 72.000 ;
+ PIN VSS
+ DIRECTION INOUT ;
+ USE GROUND ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER Metal1 ;
+ RECT 0.000 70.000 53.500 72.000 ;
+ RECT 12.500 62.000 14.500 70.000 ;
+ END
+ END VSS
+ PIN VDD
+ DIRECTION INOUT ;
+ USE POWER ;
+ SHAPE ABUTMENT ;
+ PORT
+ LAYER Metal1 ;
+ RECT 13.000 2.000 15.200 12.000 ;
+ RECT 0.000 0.000 53.500 2.000 ;
+ END
+ END VDD
+ PIN Y
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 317.519989 ;
+ PORT
+ LAYER Metal1 ;
+ RECT 12.500 55.750 20.000 58.250 ;
+ RECT 12.500 17.750 15.000 55.750 ;
+ RECT 12.500 15.250 20.500 17.750 ;
+ END
+ END Y
+ PIN A
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAGATEAREA 81.000000 ;
+ PORT
+ LAYER Metal1 ;
+ RECT 42.500 22.750 45.000 49.750 ;
+ END
+ END A
+ OBS
+ LAYER Metal1 ;
+ RECT 16.500 65.250 20.500 69.000 ;
+ RECT 15.500 64.750 21.500 65.250 ;
+ RECT 15.500 63.500 16.000 64.750 ;
+ RECT 17.250 63.500 21.500 64.750 ;
+ RECT 15.500 62.750 21.500 63.500 ;
+ RECT 17.000 9.750 21.500 10.750 ;
+ RECT 17.000 8.750 17.250 9.750 ;
+ RECT 18.500 8.750 21.500 9.750 ;
+ RECT 17.000 8.250 21.500 8.750 ;
+ RECT 16.750 4.750 20.250 8.250 ;
+ LAYER Metal2 ;
+ RECT 23.650 66.500 34.450 67.850 ;
+ RECT 22.300 65.150 34.450 66.500 ;
+ RECT 19.600 62.450 37.150 65.150 ;
+ RECT 18.250 57.050 38.500 62.450 ;
+ RECT 18.250 55.700 22.300 57.050 ;
+ RECT 18.250 54.350 20.950 55.700 ;
+ RECT 19.600 53.000 20.950 54.350 ;
+ RECT 26.350 53.000 30.400 57.050 ;
+ RECT 34.450 55.700 38.500 57.050 ;
+ RECT 35.800 54.350 38.500 55.700 ;
+ RECT 35.800 53.000 37.150 54.350 ;
+ RECT 19.600 51.650 22.300 53.000 ;
+ RECT 25.000 51.650 31.750 53.000 ;
+ RECT 34.450 51.650 37.150 53.000 ;
+ RECT 19.600 50.300 27.700 51.650 ;
+ RECT 29.050 50.300 35.800 51.650 ;
+ RECT 22.300 48.950 26.350 50.300 ;
+ RECT 30.400 48.950 35.800 50.300 ;
+ RECT 23.650 46.250 33.100 48.950 ;
+ RECT 15.550 44.900 19.600 46.250 ;
+ RECT 23.650 44.900 25.000 46.250 ;
+ RECT 26.350 44.900 27.700 46.250 ;
+ RECT 29.050 44.900 30.400 46.250 ;
+ RECT 31.750 44.900 33.100 46.250 ;
+ RECT 37.150 44.900 41.200 46.250 ;
+ RECT 14.200 42.200 20.950 44.900 ;
+ RECT 35.800 42.200 42.550 44.900 ;
+ RECT 15.550 40.850 23.650 42.200 ;
+ RECT 33.100 40.850 41.200 42.200 ;
+ RECT 19.600 39.500 25.000 40.850 ;
+ RECT 31.750 39.500 37.150 40.850 ;
+ RECT 22.300 38.150 27.700 39.500 ;
+ RECT 29.050 38.150 34.450 39.500 ;
+ RECT 25.000 35.450 31.750 38.150 ;
+ RECT 22.300 34.100 27.700 35.450 ;
+ RECT 29.050 34.100 34.450 35.450 ;
+ RECT 15.550 32.750 25.000 34.100 ;
+ RECT 31.750 32.750 42.550 34.100 ;
+ RECT 14.200 31.400 22.300 32.750 ;
+ RECT 34.450 31.400 42.550 32.750 ;
+ RECT 14.200 30.050 19.600 31.400 ;
+ RECT 37.150 30.050 42.550 31.400 ;
+ RECT 14.200 28.700 18.250 30.050 ;
+ RECT 38.500 28.700 42.550 30.050 ;
+ RECT 15.550 27.350 16.900 28.700 ;
+ RECT 23.650 27.350 25.000 28.700 ;
+ RECT 26.350 27.350 27.700 28.700 ;
+ RECT 29.050 27.350 30.400 28.700 ;
+ RECT 31.750 27.350 33.100 28.700 ;
+ RECT 39.850 27.350 41.200 28.700 ;
+ RECT 23.650 24.650 33.100 27.350 ;
+ RECT 22.300 23.300 26.350 24.650 ;
+ RECT 30.400 23.300 35.800 24.650 ;
+ RECT 19.600 21.950 27.700 23.300 ;
+ RECT 29.050 21.950 35.800 23.300 ;
+ RECT 19.600 20.600 22.300 21.950 ;
+ RECT 25.000 20.600 31.750 21.950 ;
+ RECT 34.450 20.600 37.150 21.950 ;
+ RECT 19.600 19.250 20.950 20.600 ;
+ RECT 18.250 17.900 20.950 19.250 ;
+ RECT 18.250 16.550 22.300 17.900 ;
+ RECT 26.350 16.550 30.400 20.600 ;
+ RECT 35.800 19.250 37.150 20.600 ;
+ RECT 35.800 17.900 38.500 19.250 ;
+ RECT 34.450 16.550 38.500 17.900 ;
+ RECT 18.250 11.150 38.500 16.550 ;
+ RECT 19.600 8.450 37.150 11.150 ;
+ RECT 22.300 7.100 34.450 8.450 ;
+ RECT 23.650 5.750 34.450 7.100 ;
+ END
+END skullfet_inverter
+END LIBRARY
+
diff --git a/lef/skullfet_nand.lef b/lef/skullfet_nand.lef
new file mode 100755
index 0000000..95364bc
--- /dev/null
+++ b/lef/skullfet_nand.lef
@@ -0,0 +1,258 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO skullfet_nand
+ CLASS BLOCK ;
+ FOREIGN skullfet_nand ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 81.000 BY 71.550 ;
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER Metal1 ;
+ RECT 58.050 14.850 78.300 15.525 ;
+ RECT 58.050 12.825 73.575 14.850 ;
+ RECT 76.275 12.825 78.300 14.850 ;
+ RECT 58.050 10.125 58.725 12.825 ;
+ RECT 60.750 10.125 78.300 12.825 ;
+ RECT 58.050 8.775 78.300 10.125 ;
+ RECT 75.600 2.025 78.300 8.775 ;
+ RECT 0.000 0.000 78.300 2.025 ;
+ END
+ END VPWR
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER Metal1 ;
+ RECT 4.725 12.825 15.525 13.500 ;
+ RECT 4.725 10.125 5.400 12.825 ;
+ RECT 7.425 10.125 15.525 12.825 ;
+ RECT 4.725 9.450 15.525 10.125 ;
+ RECT 4.725 5.400 7.425 9.450 ;
+ RECT 0.000 3.375 73.575 5.400 ;
+ END
+ END VGND
+ OBS
+ LAYER Metal1 ;
+ RECT 35.775 68.175 46.575 69.525 ;
+ RECT 34.425 66.825 46.575 68.175 ;
+ RECT 31.725 64.125 49.275 66.825 ;
+ RECT 30.375 58.725 50.625 64.125 ;
+ RECT 59.400 60.750 60.750 62.100 ;
+ RECT 70.200 60.750 71.550 62.100 ;
+ RECT 30.375 57.375 34.425 58.725 ;
+ RECT 30.375 56.025 33.075 57.375 ;
+ RECT 31.725 54.675 33.075 56.025 ;
+ RECT 38.475 54.675 42.525 58.725 ;
+ RECT 46.575 57.375 50.625 58.725 ;
+ RECT 47.925 56.025 50.625 57.375 ;
+ RECT 47.925 54.675 49.275 56.025 ;
+ RECT 31.725 53.325 34.425 54.675 ;
+ RECT 37.125 53.325 43.875 54.675 ;
+ RECT 46.575 53.325 49.275 54.675 ;
+ RECT 31.725 51.975 39.825 53.325 ;
+ RECT 41.175 51.975 47.925 53.325 ;
+ RECT 34.425 50.625 38.475 51.975 ;
+ RECT 42.525 50.625 47.925 51.975 ;
+ RECT 7.425 47.925 15.525 49.275 ;
+ RECT 35.775 47.925 45.225 50.625 ;
+ RECT 65.475 47.925 73.575 49.275 ;
+ RECT 4.725 46.575 18.225 47.925 ;
+ RECT 27.675 46.575 31.725 47.925 ;
+ RECT 35.775 46.575 37.125 47.925 ;
+ RECT 38.475 46.575 39.825 47.925 ;
+ RECT 41.175 46.575 42.525 47.925 ;
+ RECT 43.875 46.575 45.225 47.925 ;
+ RECT 49.275 46.575 53.325 47.925 ;
+ RECT 61.425 46.575 76.275 47.925 ;
+ RECT 4.725 45.225 14.175 46.575 ;
+ RECT 16.875 45.225 20.925 46.575 ;
+ RECT 2.025 41.175 12.825 45.225 ;
+ RECT 18.225 43.875 20.925 45.225 ;
+ RECT 26.325 43.875 33.075 46.575 ;
+ RECT 47.925 43.875 54.675 46.575 ;
+ RECT 61.425 45.225 64.125 46.575 ;
+ RECT 66.825 45.225 76.275 46.575 ;
+ RECT 60.075 43.875 62.775 45.225 ;
+ RECT 18.225 42.525 24.975 43.875 ;
+ RECT 27.675 42.525 35.775 43.875 ;
+ RECT 45.225 42.525 53.325 43.875 ;
+ RECT 56.025 42.525 62.775 43.875 ;
+ RECT 68.175 43.875 77.625 45.225 ;
+ RECT 16.875 41.175 23.625 42.525 ;
+ RECT 31.725 41.175 37.125 42.525 ;
+ RECT 43.875 41.175 49.275 42.525 ;
+ RECT 57.375 41.175 64.125 42.525 ;
+ RECT 68.175 41.175 78.975 43.875 ;
+ RECT 2.025 39.825 19.575 41.175 ;
+ RECT 20.925 39.825 24.975 41.175 ;
+ RECT 34.425 39.825 39.825 41.175 ;
+ RECT 41.175 39.825 46.575 41.175 ;
+ RECT 56.025 39.825 60.075 41.175 ;
+ RECT 61.425 39.825 78.975 41.175 ;
+ RECT 2.025 38.475 18.225 39.825 ;
+ RECT 20.925 38.475 23.625 39.825 ;
+ RECT 2.025 37.125 19.575 38.475 ;
+ RECT 20.925 37.125 24.975 38.475 ;
+ RECT 37.125 37.125 43.875 39.825 ;
+ RECT 57.375 38.475 60.075 39.825 ;
+ RECT 62.775 38.475 78.975 39.825 ;
+ RECT 56.025 37.125 60.075 38.475 ;
+ RECT 61.425 37.125 78.975 38.475 ;
+ RECT 2.025 34.425 12.825 37.125 ;
+ RECT 16.875 35.775 23.625 37.125 ;
+ RECT 34.425 35.775 39.825 37.125 ;
+ RECT 41.175 35.775 46.575 37.125 ;
+ RECT 57.375 35.775 64.125 37.125 ;
+ RECT 3.375 33.075 12.825 34.425 ;
+ RECT 18.225 34.425 24.975 35.775 ;
+ RECT 27.675 34.425 37.125 35.775 ;
+ RECT 43.875 34.425 54.675 35.775 ;
+ RECT 56.025 34.425 62.775 35.775 ;
+ RECT 18.225 33.075 20.925 34.425 ;
+ RECT 26.325 33.075 34.425 34.425 ;
+ RECT 46.575 33.075 54.675 34.425 ;
+ RECT 4.725 31.725 14.175 33.075 ;
+ RECT 16.875 31.725 19.575 33.075 ;
+ RECT 2.025 29.025 3.375 31.050 ;
+ RECT 4.725 30.375 19.575 31.725 ;
+ RECT 26.325 31.725 31.725 33.075 ;
+ RECT 49.275 31.725 54.675 33.075 ;
+ RECT 60.075 33.075 62.775 34.425 ;
+ RECT 68.175 33.075 78.975 37.125 ;
+ RECT 60.075 31.725 64.125 33.075 ;
+ RECT 66.825 31.725 76.275 33.075 ;
+ RECT 26.325 30.375 30.375 31.725 ;
+ RECT 50.625 30.375 54.675 31.725 ;
+ RECT 62.775 30.375 76.275 31.725 ;
+ RECT 7.425 29.025 15.525 30.375 ;
+ RECT 27.675 29.025 29.025 30.375 ;
+ RECT 35.775 29.025 37.125 30.375 ;
+ RECT 38.475 29.025 39.825 30.375 ;
+ RECT 41.175 29.025 42.525 30.375 ;
+ RECT 43.875 29.025 45.225 30.375 ;
+ RECT 51.975 29.025 53.325 30.375 ;
+ RECT 65.475 29.025 73.575 30.375 ;
+ RECT 77.625 29.025 78.975 31.050 ;
+ RECT 35.775 26.325 45.225 29.025 ;
+ RECT 34.425 24.975 38.475 26.325 ;
+ RECT 42.525 24.975 47.925 26.325 ;
+ RECT 31.725 23.625 39.825 24.975 ;
+ RECT 41.175 23.625 47.925 24.975 ;
+ RECT 31.725 22.275 34.425 23.625 ;
+ RECT 37.125 22.275 43.875 23.625 ;
+ RECT 46.575 22.275 49.275 23.625 ;
+ RECT 31.725 20.925 33.075 22.275 ;
+ RECT 30.375 19.575 33.075 20.925 ;
+ RECT 30.375 18.225 34.425 19.575 ;
+ RECT 38.475 18.225 42.525 22.275 ;
+ RECT 47.925 20.925 49.275 22.275 ;
+ RECT 47.925 19.575 50.625 20.925 ;
+ RECT 46.575 18.225 50.625 19.575 ;
+ RECT 9.450 14.850 10.800 16.200 ;
+ RECT 20.250 14.850 21.600 16.200 ;
+ RECT 30.375 12.825 50.625 18.225 ;
+ RECT 31.725 10.125 49.275 12.825 ;
+ RECT 34.425 8.775 46.575 10.125 ;
+ RECT 35.775 7.425 46.575 8.775 ;
+ RECT 48.600 7.425 50.625 8.775 ;
+ LAYER Metal2 ;
+ RECT 35.775 68.175 46.575 69.525 ;
+ RECT 34.425 66.825 46.575 68.175 ;
+ RECT 31.725 64.125 49.275 66.825 ;
+ RECT 30.375 58.725 50.625 64.125 ;
+ RECT 30.375 57.375 34.425 58.725 ;
+ RECT 30.375 56.025 33.075 57.375 ;
+ RECT 31.725 54.675 33.075 56.025 ;
+ RECT 38.475 54.675 42.525 58.725 ;
+ RECT 46.575 57.375 50.625 58.725 ;
+ RECT 47.925 56.025 50.625 57.375 ;
+ RECT 47.925 54.675 49.275 56.025 ;
+ RECT 31.725 53.325 34.425 54.675 ;
+ RECT 37.125 53.325 43.875 54.675 ;
+ RECT 46.575 53.325 49.275 54.675 ;
+ RECT 31.725 51.975 39.825 53.325 ;
+ RECT 41.175 51.975 47.925 53.325 ;
+ RECT 34.425 50.625 38.475 51.975 ;
+ RECT 42.525 50.625 47.925 51.975 ;
+ RECT 7.425 47.925 15.525 49.275 ;
+ RECT 35.775 47.925 45.225 50.625 ;
+ RECT 65.475 47.925 73.575 49.275 ;
+ RECT 4.725 46.575 18.225 47.925 ;
+ RECT 35.775 46.575 37.125 47.925 ;
+ RECT 38.475 46.575 39.825 47.925 ;
+ RECT 41.175 46.575 42.525 47.925 ;
+ RECT 43.875 46.575 45.225 47.925 ;
+ RECT 61.425 46.575 76.275 47.925 ;
+ RECT 4.725 45.225 14.175 46.575 ;
+ RECT 16.875 45.225 20.925 46.575 ;
+ RECT 61.425 45.225 64.125 46.575 ;
+ RECT 66.825 45.225 76.275 46.575 ;
+ RECT 2.025 41.175 12.825 45.225 ;
+ RECT 18.225 43.875 20.925 45.225 ;
+ RECT 60.075 43.875 62.775 45.225 ;
+ RECT 18.225 42.525 24.975 43.875 ;
+ RECT 56.025 42.525 62.775 43.875 ;
+ RECT 68.175 43.875 77.625 45.225 ;
+ RECT 16.875 41.175 23.625 42.525 ;
+ RECT 57.375 41.175 64.125 42.525 ;
+ RECT 68.175 41.175 78.975 43.875 ;
+ RECT 2.025 39.825 19.575 41.175 ;
+ RECT 20.925 39.825 24.975 41.175 ;
+ RECT 56.025 39.825 60.075 41.175 ;
+ RECT 61.425 39.825 78.975 41.175 ;
+ RECT 2.025 38.475 18.225 39.825 ;
+ RECT 20.925 38.475 23.625 39.825 ;
+ RECT 57.375 38.475 60.075 39.825 ;
+ RECT 62.775 38.475 78.975 39.825 ;
+ RECT 2.025 37.125 19.575 38.475 ;
+ RECT 20.925 37.125 24.975 38.475 ;
+ RECT 56.025 37.125 60.075 38.475 ;
+ RECT 61.425 37.125 78.975 38.475 ;
+ RECT 2.025 34.425 12.825 37.125 ;
+ RECT 16.875 35.775 23.625 37.125 ;
+ RECT 57.375 35.775 64.125 37.125 ;
+ RECT 3.375 33.075 12.825 34.425 ;
+ RECT 18.225 34.425 24.975 35.775 ;
+ RECT 56.025 34.425 62.775 35.775 ;
+ RECT 18.225 33.075 20.925 34.425 ;
+ RECT 60.075 33.075 62.775 34.425 ;
+ RECT 68.175 33.075 78.975 37.125 ;
+ RECT 4.725 31.725 14.175 33.075 ;
+ RECT 16.875 31.725 19.575 33.075 ;
+ RECT 60.075 31.725 64.125 33.075 ;
+ RECT 66.825 31.725 76.275 33.075 ;
+ RECT 4.725 30.375 19.575 31.725 ;
+ RECT 62.775 30.375 76.275 31.725 ;
+ RECT 7.425 29.025 15.525 30.375 ;
+ RECT 35.775 29.025 37.125 30.375 ;
+ RECT 38.475 29.025 39.825 30.375 ;
+ RECT 41.175 29.025 42.525 30.375 ;
+ RECT 43.875 29.025 45.225 30.375 ;
+ RECT 65.475 29.025 73.575 30.375 ;
+ RECT 35.775 26.325 45.225 29.025 ;
+ RECT 34.425 24.975 38.475 26.325 ;
+ RECT 42.525 24.975 47.925 26.325 ;
+ RECT 31.725 23.625 39.825 24.975 ;
+ RECT 41.175 23.625 47.925 24.975 ;
+ RECT 31.725 22.275 34.425 23.625 ;
+ RECT 37.125 22.275 43.875 23.625 ;
+ RECT 46.575 22.275 49.275 23.625 ;
+ RECT 31.725 20.925 33.075 22.275 ;
+ RECT 30.375 19.575 33.075 20.925 ;
+ RECT 30.375 18.225 34.425 19.575 ;
+ RECT 38.475 18.225 42.525 22.275 ;
+ RECT 47.925 20.925 49.275 22.275 ;
+ RECT 47.925 19.575 50.625 20.925 ;
+ RECT 46.575 18.225 50.625 19.575 ;
+ RECT 30.375 12.825 50.625 18.225 ;
+ RECT 31.725 10.125 49.275 12.825 ;
+ RECT 34.425 8.775 46.575 10.125 ;
+ RECT 35.775 7.425 46.575 8.775 ;
+ END
+END skullfet_nand
+END LIBRARY
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index df19160..fda25e1 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -36,7 +36,7 @@
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) "mprj.clk"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "100"
## Internal Macros
### Macro PDN Connections
@@ -49,13 +49,11 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/skullfet.v"
-set ::env(EXTRA_LEFS) "\
- $::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
+set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/../../lef/skullfet_*.lef]
-set ::env(EXTRA_GDS_FILES) "\
- $::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
+set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/../../gds/skullfet_*.gds]
set ::env(RT_MAX_LAYER) {Metal4}
@@ -64,8 +62,8 @@
set ::env(FP_PDN_CHECK_NODES) 0
# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_ELABORATE_ONLY) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+#set ::env(SYNTH_ELABORATE_ONLY) 1
+#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..568caba 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+inv1 1125 1690 N
diff --git a/verilog/rtl/skullfet.v b/verilog/rtl/skullfet.v
new file mode 100644
index 0000000..a4dd35e
--- /dev/null
+++ b/verilog/rtl/skullfet.v
@@ -0,0 +1,22 @@
+(* blackbox *)
+module skullfet_inverter (
+`ifdef USE_POWER_PINS
+ input VSS,
+ input VDD,
+`endif // USE_POWER_PINS
+ input A,
+ output Y
+);
+endmodule
+
+(* blackbox *)
+module skullfet_nand (
+`ifdef USE_POWER_PINS
+ input VSS,
+ input VDD,
+`endif // USE_POWER_PINS
+ input A,
+ input B,
+ output Y
+);
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 146877d..f213bf7 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -70,40 +70,14 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+skullfet_inverter inv1 (
`ifdef USE_POWER_PINS
- .vdd(vdd), // User area 1 1.8V power
- .vss(vss), // User area 1 digital ground
+ .VDD(vdd), // User area 1 5V power
+ .VSS(vss), // User area 1 digital ground
`endif
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
+ .A(io_in[8]),
+ .Y(io_out[16])
);
endmodule // user_project_wrapper
