feat: configure for wokwi project
- update info.yaml with Wokwi project id
- update pin configuration in info.yaml / user_defines.v
diff --git a/configure.py b/configure.py
index ff5d954..3a62dc9 100755
--- a/configure.py
+++ b/configure.py
@@ -26,7 +26,7 @@
// pass input and output pins defined in user_defines.v
{module_name} mod (
- io_in[19:12],
+ io_in[19:8],
io_out[27:20]
);
// all output enabled
diff --git a/info.yaml b/info.yaml
index a597d9e..9edcc72 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,7 +1,7 @@
---
# TinyTapeout project information
project:
- wokwi_id: 334445762078310996 # If using wokwi, set this to your project's ID
+ wokwi_id: 349466952232600147 # If using wokwi, set this to your project's ID
# source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src
# - counter.v
# - decoder.v
@@ -14,9 +14,9 @@
#
# This info will be automatically collected and used to make a datasheet for the chip.
documentation:
- author: "" # Your name
- discord: "" # Your discord handle - make sure to include the # part as well
- title: "" # Project title
+ author: "Uri Shaked (Wokwi)" # Your name
+ discord: "urish#8086" # Your discord handle - make sure to include the # part as well
+ title: "Game of Life - Cell" # Project title
description: "" # Short description of what your project does
how_it_works: "" # Longer description of how the project works
how_to_test: "" # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
@@ -26,21 +26,24 @@
clock_hz: 0 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
picture: "" # relative path to a picture in your repository
inputs: # a description of what the inputs do
- - clock
- - reset
- - none
- - none
- - none
- - none
- - none
+ - n0
+ - n1
+ - n2
+ - n3
+ - n4
+ - n5
+ - n6
+ - n7
+ - clk
+ - rst
+ - force
- none
outputs:
- - segment a # a description of what the outputs do
- - segment b
- - segment c
- - segment d
- - segment e
- - segment f
- - segment g
+ - alive
+ - not_alive
- none
-
+ - none
+ - none
+ - none
+ - none
+ - none
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index 7a38e03..b8061b3 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -55,12 +55,12 @@
`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_INVALID
// tinytapeout project input
+`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
