verilog/rtl/tiny_user_project.v

// generated by configure.py
`default_nettype none

module tiny_user_project(
  input [`MPRJ_IO_PADS-1:0] io_in,
  output [`MPRJ_IO_PADS-1:0] io_out,
  output [`MPRJ_IO_PADS-1:0] io_oeb
);

// pass input and output pins defined in user_defines.v
user_module_349472166361694804 mod (
    io_in[19:9],
    io_out[27:20]
);
// all output enabled
assign io_oeb[27:20] = 8'b0;

endmodule	// tiny_user_project

`default_nettype wire