fix: only use 11 I/O pins (to match Wokwi design)
diff --git a/configure.py b/configure.py
index 3a62dc9..726c2b7 100755
--- a/configure.py
+++ b/configure.py
@@ -26,7 +26,7 @@
// pass input and output pins defined in user_defines.v
{module_name} mod (
- io_in[19:8],
+ io_in[19:9],
io_out[27:20]
);
// all output enabled
diff --git a/info.yaml b/info.yaml
index 9edcc72..a213d67 100644
--- a/info.yaml
+++ b/info.yaml
@@ -37,7 +37,6 @@
- clk
- rst
- force
- - none
outputs:
- alive
- not_alive
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index b8061b3..6088f27 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -55,9 +55,9 @@
`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID
+`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_INVALID
// tinytapeout project input
-`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
