bf540bcdad01a15ea399a3befdc74785cf367e59 - third_party/shuttle/gf180mcu/mpw-000/slot-008

commit: bf540bcdad01a15ea399a3befdc74785cf367e59
[log]
author: gatecat <gatecat@ds0.me>
Wed Nov 30 16:19:16 2022 +0100
committer: gatecat <gatecat@ds0.me>
Sun Dec 04 21:10:33 2022 +0100
tree: d56c240e2dadd5c7146c67b4ede33aa2231beb9c
parent: 64448e099aa5bb60623fd445ab62181d7847bb75 [diff]

initial GDS

Signed-off-by: gatecat <gatecat@ds0.me>

Makefile[diff]
README.md[diff]
gds/user_project_wrapper.gds[diff]
openlane/Makefile[diff]
openlane/user_project_wrapper/bitcell/gf180mcu_fpga_bitmux.gds[Added - diff]
openlane/user_project_wrapper/bitcell/gf180mcu_fpga_bitmux.lef[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/macros/gds/E_IO.gds[Added - diff]
openlane/user_project_wrapper/macros/gds/LUT4AB.gds[Added - diff]
openlane/user_project_wrapper/macros/gds/N_term_single.gds[Added - diff]
openlane/user_project_wrapper/macros/gds/S_term_single.gds[Added - diff]
openlane/user_project_wrapper/macros/gds/W_IO.gds[Added - diff]
openlane/user_project_wrapper/macros/lef/E_IO.lef[Added - diff]
openlane/user_project_wrapper/macros/lef/LUT4AB.lef[Added - diff]
openlane/user_project_wrapper/macros/lef/N_term_single.lef[Added - diff]
openlane/user_project_wrapper/macros/lef/S_term_single.lef[Added - diff]
openlane/user_project_wrapper/macros/lef/W_IO.lef[Added - diff]
openlane/user_project_wrapper/macros/verilog/E_IO_tile.v[Added - diff]
openlane/user_project_wrapper/macros/verilog/LUT4AB_tile.v[Added - diff]
openlane/user_project_wrapper/macros/verilog/N_term_single_tile.v[Added - diff]
openlane/user_project_wrapper/macros/verilog/S_term_single_tile.v[Added - diff]
openlane/user_project_wrapper/macros/verilog/W_IO_tile.v[Added - diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/eFPGA_top.v[Added - diff]
verilog/rtl/fabric.v[Added - diff]
verilog/rtl/models_pack.v[Added - diff]
verilog/rtl/user_defines.v[diff]
verilog/rtl/wrapper_gf180.v[Added - diff]

31 files changed

tree: d56c240e2dadd5c7146c67b4ede33aa2231beb9c

README.md

FABulous test on GF180 with custom one-hot SRAM+transmission gate element for routing