commit	2c26c3c2367f1402f516dc6d64aaf43e31f2a00e	[log] [tgz]
author	Cra2yPierr0t <uchiyama.kazuhide@gmail.com>	Fri Dec 02 05:19:00 2022 +0900
committer	Cra2yPierr0t <uchiyama.kazuhide@gmail.com>	Fri Dec 02 05:19:00 2022 +0900
tree	d24f1b855fb66052bbe3be2d9c28e298391dcdef
parent	d59ff858c39378cbec281ea11988f4fb447e7a20 [diff]

first commit

openlane/computer/config.json[Added - diff]
openlane/computer/config.tcl[Added - diff]
openlane/computer/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.json[diff]
openlane/user_project_wrapper/macro.cfg[diff]
verilog/rtl/jacaranda-8/UART/UART.v[Added - diff]
verilog/rtl/jacaranda-8/UART/rx.v[Added - diff]
verilog/rtl/jacaranda-8/UART/tx.v[Added - diff]
verilog/rtl/jacaranda-8/alu.v[Added - diff]
verilog/rtl/jacaranda-8/alu_controller.v[Added - diff]
verilog/rtl/jacaranda-8/computer.v[Added - diff]
verilog/rtl/jacaranda-8/cpu.v[Added - diff]
verilog/rtl/jacaranda-8/data_mem.v[Added - diff]
verilog/rtl/jacaranda-8/decoder.v[Added - diff]
verilog/rtl/jacaranda-8/instr_mem.v[Added - diff]
verilog/rtl/jacaranda-8/main_controller.v[Added - diff]
verilog/rtl/jacaranda-8/regfile.v[Added - diff]
verilog/rtl/jacaranda-8/wishbone.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]

19 files changed

tree: d24f1b855fb66052bbe3be2d9c28e298391dcdef

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.