Merge branch 'main' of https://github.com/H-S-S-11/gf180-mpw0
diff --git a/info.yaml b/info.yaml
index 3b00768..b20c21b 100644
--- a/info.yaml
+++ b/info.yaml
@@ -33,19 +33,22 @@
inputs: # a description of what the inputs do
- clock
- reset
- - none
- - none
- - none
- - none
- - none
- - none
+ - write_en
+ - pdm_input[0]
+ - pdm_input[1]
+ - pdm_input[2]
+ - pdm_input[3]
+ - pdm_input[4]
+ - dice_clock
+ - dice_reset
outputs:
- - segment a # a description of what the outputs do
- - segment b
- - segment c
- - segment d
- - segment e
- - segment f
- - segment g
- - none
+ - pdm_out # a description of what the outputs do
+ - n_pdm_out
+ - TL
+ - ML
+ - BL
+ - MC
+ - TR
+ - MR
+ - BR
diff --git a/verilog/rtl/pdm.v b/verilog/rtl/pdm.v
index 68ba105..55b99dd 100644
--- a/verilog/rtl/pdm.v
+++ b/verilog/rtl/pdm.v
@@ -1,4 +1,4 @@
-// 8-bit PDM driver
+// 5-bit PDM driver
module pdm(
input [4:0] pdm_input,
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index a6dad2d..e36f6c8 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -4,7 +4,6 @@
// The pin connections within the user_module can change
// This allows use of the internal clock divider if you wish.
module user_module(
- input user_clock2,
input [18:0] io_in,
output [18:0] io_out
);
