blob: b20c21bf0ff2ee67f6dcf5c5579da2d4a7fd776c [file] [log] [blame]
# TinyTapeout project information
wokwi_id: 0
source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
- verilog/rtl/user_module.v
- verilog/rtl/pdm.v
- verilog/rtl/dice.v
- verilog/rtl/dtype_synth.v
- verilog/rtl/encoder.v
- verilog/rtl/control.v
- verilog/rtl/random.v
top_module: "user_module" # put the name of your top module here, make it unique by prepending your github username
# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
# it does and how to operate it.
# Here is an example:
# This info will be automatically collected and used to make a datasheet for the chip.
author: "Harry Snell" # Your name
discord: "dub_dub_11#8141" # Your discord handle - make sure to include the # part as well
title: "GF180 verilog test" # Project title
description: "PDM driver and dice module with 7 seg display" # Short description of what your project does
how_it_works: "" # Longer description of how the project works
how_to_test: "" # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
external_hw: "" # Describe any external hardware needed
language: "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
doc_link: "" # URL to longer form documentation, eg the in your repository
clock_hz: 0 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
picture: "" # relative path to a picture in your repository
inputs: # a description of what the inputs do
- clock
- reset
- write_en
- pdm_input[0]
- pdm_input[1]
- pdm_input[2]
- pdm_input[3]
- pdm_input[4]
- dice_clock
- dice_reset
- pdm_out # a description of what the outputs do
- n_pdm_out
- TL
- ML
- BL
- MC
- TR
- MR
- BR