commit 886bd06779e553ee574770bcff5afd210a0e6a4a
author H-S-S-11 <harry.saxon.snell@gmail.com> Sat Dec 03 01:31:48 2022 +0000
committer H-S-S-11 <harry.saxon.snell@gmail.com> Sat Dec 03 01:31:48 2022 +0000
tree 0374ef5cbd077d1c3304513a926021b1d1a8777c
parent 62ead149081a6122e73ba85bfb6f3112655912ef

remove timeunit

verilog/rtl/random.v

diff --git a/verilog/rtl/random.v b/verilog/rtl/random.v
index cf9a328..c96b103 100644
--- a/verilog/rtl/random.v
+++ b/verilog/rtl/random.v
@@ -1,7 +1,5 @@
 // SystemVerilog structural model of a LFSR PRBS generator
 
-timeunit 1ns; timeprecision 10ps;
-
 module random(
   input wire Clock, nReset,
   output wire [1:0] Ran