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gf180mcu
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mpw-000
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slot-005
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62ead149081a6122e73ba85bfb6f3112655912ef
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.
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verilog
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rtl
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dtype_synth.v
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// structural model of edge triggered D type
module
dtype
(
output logic Q
,
nQ
,
input wire D
,
Clk
,
nRst
);
always@
(
posedge
Clk
,
negedge nRst
)
begin
if
(~
nRst
)
begin
Q
<=
1
'b0;
nQ <= 1'
b1
;
end
else
begin
Q
<=
D
;
nQ
<=
~
D
;
end
end
endmodule