add pdm code
diff --git a/info.yaml b/info.yaml index 8e04ea5..fef0d8b 100644 --- a/info.yaml +++ b/info.yaml
@@ -5,7 +5,7 @@ source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here - verilog/rtl/counter.v - verilog/rtl/decoder.v - top_module: "seven_segment_seconds" # put the name of your top module here, make it unique by prepending your github username + top_module: "user_module" # put the name of your top module here, make it unique by prepending your github username # As everyone will have access to all designs, try to make it easy for someone new to your design to know what # it does and how to operate it.
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v index aea8267..714c20a 100644 --- a/verilog/rtl/user_module.v +++ b/verilog/rtl/user_module.v
@@ -1,88 +1,56 @@ -/* Automatically generated from https://wokwi.com/projects/334445762078310996 */ - -`default_nettype none - -module user_module_334445762078310996( - input [7:0] io_in, - output [7:0] io_out -); - wire net1 = 1'b1; - wire net2 = 1'b0; - wire net3; - wire net4; - wire net5; - wire net6; - wire net7; - wire net8 = 1'b1; - wire net9 = 1'b0; - wire net10; - wire net11; - wire net12 = 1'b1; - wire net13 = 1'b0; - wire net14; - wire net15 = 1'b1; - wire net16 = 1'b0; - wire net17; - wire net18 = 1'b0; - wire net19 = 1'b1; - wire net20; - wire net21 = 1'b1; - wire net22; - wire net23; - wire net24 = 1'b0; - wire net25 = 1'b0; - - and_cell gate1 ( - .a (net3) - ); - or_cell gate2 ( - - ); - xor_cell gate3 ( - - ); - nand_cell gate4 ( - .a (net4), - .b (net5), - .out (net6) - ); - not_cell gate5 ( - .in (net7), - .out (net5) - ); - buffer_cell gate6 ( - - ); - mux_cell mux1 ( - .a (net8), - .b (net9), - .sel (net10), - .out (net11) - ); - dff_cell flipflop1 ( - - ); - mux_cell mux2 ( - .a (net12), - .b (net13), - .sel (net10), - .out (net14) - ); - mux_cell mux3 ( - .a (net15), - .b (net16), - .sel (net10), - .out (net17) - ); - mux_cell mux4 ( - .a (net18), - .b (net19), - .sel (net10), - .out (net20) - ); - and_cell gate7 ( - .a (net22), - .b (net23), - .out (net4) - ); -endmodule +`default_nettype none + +// Top level io for this module should stay the same to fit into the scan_wrapper. +// The pin connections within the user_module are up to you, +// although (if one is present) it is recommended to place a clock on io_in[0]. +// This allows use of the internal clock divider if you wish. +module user_module( + input [7:0] io_in, + output [7:0] io_out +); + + wire pdm_out; + + assign io_out[0] = pdm_out; + assign io_out[1] = ~pdm_out; + + pdm pdm_core( + .pdm_input(io_in[7:3]), + .write_en(io_in[2]), + .reset(io_in[1]), + .clk(io_in[0]), + .pdm_out(pdm_out) + ); + +endmodule + +// Any submodules should be included in this file, +// so they are copied into the main TinyTapeout repo. +// Appending your ID to any submodules you create +// ensures there are no clashes in full-chip simulation. +module pdm( + input [4:0] pdm_input, + input write_en, + input clk, reset, + output pdm_out +); + +reg [4:0] accumulator; +reg [4:0] input_reg; + +wire [5:0] sum; + +assign sum = input_reg + accumulator; +assign pdm_out = sum[5]; + +always @(posedge clk or posedge reset) begin + if (reset) begin + input_reg <= 5'h00 ; + accumulator <= 5'h00; + end else begin + accumulator <= sum[4:0]; + if (write_en) input_reg <= pdm_input ; + end +end + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/user_module_tb.v b/verilog/rtl/user_module_tb.v new file mode 100644 index 0000000..77d4c7b --- /dev/null +++ b/verilog/rtl/user_module_tb.v
@@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +//`include "user_module.v" + +module user_module_tb; + +wire [7:0] io_in; +wire [7:0] io_out; + +reg clk, reset, write_en; +reg [4:0] pdm_input; + +assign io_in = {pdm_input, write_en, reset, clk}; + +user_module UUT (.io_in(io_in), .io_out(io_out)); + +initial begin + $dumpfile("user_module_tb.vcd"); + $dumpvars(0, user_module_tb); +end + +initial begin + #100_000_000; // Wait a long time in simulation units (adjust as needed). + $display("Caught by trap"); + $finish; + end + +parameter CLK_HALF_PERIOD = 5; +parameter TCLK = 2*CLK_HALF_PERIOD; +always begin + clk = 1'b1; + #(CLK_HALF_PERIOD); + clk = 1'b0; + #(CLK_HALF_PERIOD); +end + +initial +begin + #20 + reset = 1; + #(CLK_HALF_PERIOD); + reset = 0; +end + +initial begin + write_en = 0; + pdm_input = 5'h00; + #(CLK_HALF_PERIOD); + #(5*TCLK) + write_en = 1; + pdm_input= 5'h08; + #(TCLK); + write_en = 0; + #(63*TCLK); + write_en = 1; + pdm_input= 5'h1a; + #(TCLK); + write_en = 0; + #(63*TCLK); + write_en = 1; + pdm_input= 5'h0f; + #(64*TCLK); + pdm_input= 5'h04; + #(64*TCLK); + $finish; +end + +endmodule
diff --git a/verilog/rtl/wokwi_diagram.json b/verilog/rtl/wokwi_diagram.json deleted file mode 100644 index 357c5bd..0000000 --- a/verilog/rtl/wokwi_diagram.json +++ /dev/null
@@ -1,167 +0,0 @@ -{ - "version": 1, - "author": "Uri Shaked", - "editor": "wokwi", - "parts": [ - { - "type": "wokwi-dip-switch-8", - "id": "sw1", - "top": 31.3, - "left": -45.8, - "rotate": 90, - "attrs": {} - }, - { "type": "wokwi-vcc", "id": "pwr1", "top": -124.04, "left": -134.4, "attrs": {} }, - { "type": "wokwi-gnd", "id": "gnd1", "top": 67.2, "left": 681, "attrs": {} }, - { "type": "wokwi-gate-and-2", "id": "gate1", "top": -211.2, "left": -96, "attrs": {} }, - { "type": "wokwi-gate-or-2", "id": "gate2", "top": -276.8, "left": 148.67, "attrs": {} }, - { "type": "wokwi-gate-xor-2", "id": "gate3", "top": -276.8, "left": 13.2, "attrs": {} }, - { "type": "wokwi-gate-nand-2", "id": "gate4", "top": 364.8, "left": 201.6, "attrs": {} }, - { "type": "wokwi-gate-not", "id": "gate5", "top": 393.6, "left": 96, "attrs": {} }, - { "type": "wokwi-gate-buffer", "id": "gate6", "top": -181.2, "left": 55.2, "attrs": {} }, - { "type": "wokwi-mux-2", "id": "mux1", "top": -67.2, "left": 86.4, "attrs": {} }, - { - "type": "wokwi-flip-flop-d", - "id": "flipflop1", - "top": -323.6, - "left": -244.13, - "attrs": {} - }, - { - "type": "wokwi-clock-generator", - "id": "clkgen1", - "top": -256.93, - "left": -250, - "attrs": {} - }, - { - "type": "wokwi-led-bar-graph", - "id": "bargraph1", - "top": -62.4, - "left": 600, - "attrs": { "color": "lime" } - }, - { "type": "wokwi-vcc", "id": "pwr2", "top": -124.04, "left": 57.6, "attrs": {} }, - { "type": "wokwi-vcc", "id": "pwr3", "top": -268.04, "left": -28.8, "attrs": {} }, - { "type": "wokwi-gnd", "id": "gnd2", "top": -18.71, "left": 76.2, "attrs": {} }, - { "type": "wokwi-mux-2", "id": "mux2", "top": -9.6, "left": 172.8, "attrs": {} }, - { "type": "wokwi-mux-2", "id": "mux3", "top": 57.6, "left": 240, "attrs": {} }, - { "type": "wokwi-mux-2", "id": "mux4", "top": 144, "left": 326.4, "attrs": {} }, - { "type": "wokwi-vcc", "id": "pwr4", "top": 19.96, "left": 230.4, "attrs": {} }, - { "type": "wokwi-vcc", "id": "pwr5", "top": 165.84, "left": 317, "rotate": 180, "attrs": {} }, - { "type": "wokwi-vcc", "id": "pwr6", "top": -37.64, "left": 163.2, "attrs": {} }, - { "type": "wokwi-gnd", "id": "gnd3", "top": 28.8, "left": 162.6, "attrs": {} }, - { "type": "wokwi-gnd", "id": "gnd4", "top": 96, "left": 229.8, "attrs": {} }, - { "type": "wokwi-gnd", "id": "gnd5", "top": 101, "left": 325.2, "rotate": 180, "attrs": {} }, - { - "type": "wokwi-dip-switch-8", - "id": "sw2", - "top": 342.76, - "left": -65.04, - "rotate": 90, - "attrs": {} - }, - { "type": "wokwi-vcc", "id": "pwr7", "top": 298.36, "left": -67.2, "attrs": {} }, - { "type": "wokwi-gate-and-2", "id": "gate7", "top": 326.4, "left": 96, "attrs": {} }, - { - "type": "wokwi-resistor", - "id": "r1", - "top": -27.98, - "left": 9.21, - "rotate": 90, - "attrs": { "value": "1000" } - }, - { - "type": "wokwi-gnd", - "id": "gnd7", - "top": -95.97, - "left": -1.54, - "rotate": 180, - "attrs": {} - }, - { - "type": "wokwi-resistor", - "id": "r2", - "top": 278.2, - "left": -2.2, - "rotate": 90, - "attrs": { "value": "1000" } - }, - { - "type": "wokwi-resistor", - "id": "r3", - "top": 278.2, - "left": 26.6, - "rotate": 90, - "attrs": { "value": "1000" } - }, - { - "type": "wokwi-resistor", - "id": "r4", - "top": 278.2, - "left": 55.4, - "rotate": 90, - "attrs": { "value": "1000" } - }, - { "type": "wokwi-gnd", "id": "gnd8", "top": 216.2, "left": 47.8, "rotate": 180, "attrs": {} } - ], - "connections": [ - [ "mux1:OUT", "bargraph1:A1", "green", [ "v0" ] ], - [ "pwr1:VCC", "sw1:1a", "red", [ "v0" ] ], - [ "pwr2:VCC", "mux1:A", "red", [ "v0" ] ], - [ "mux1:B", "gnd2:GND", "green", [ "h0" ] ], - [ "bargraph1:C1", "bargraph1:C2", "green", [ "v0" ] ], - [ "bargraph1:C2", "bargraph1:C3", "green", [ "h0" ] ], - [ "bargraph1:C3", "bargraph1:C4", "green", [ "h0" ] ], - [ "bargraph1:C4", "bargraph1:C5", "green", [ "h0" ] ], - [ "bargraph1:C5", "bargraph1:C6", "green", [ "h0" ] ], - [ "bargraph1:C6", "bargraph1:C7", "green", [ "h0" ] ], - [ "bargraph1:C7", "bargraph1:C8", "green", [ "h0" ] ], - [ "bargraph1:C8", "bargraph1:C9", "green", [ "h0" ] ], - [ "bargraph1:C10", "bargraph1:C9", "green", [ "h0" ] ], - [ "bargraph1:C10", "gnd1:GND", "green", [ "h0" ] ], - [ "sw1:1b", "mux1:SEL", "green", [ "h0" ] ], - [ "pwr6:VCC", "mux2:A", "red", [ "v0" ] ], - [ "gnd3:GND", "mux2:B", "black", [ "v0" ] ], - [ "pwr4:VCC", "mux3:A", "red", [ "v0" ] ], - [ "gnd4:GND", "mux3:B", "black", [ "v0" ] ], - [ "gnd5:GND", "mux4:A", "black", [ "v0" ] ], - [ "pwr5:VCC", "mux4:B", "red", [ "v0" ] ], - [ "sw1:1b", "mux2:SEL", "green", [ "h0" ] ], - [ "sw1:1b", "mux3:SEL", "green", [ "h0" ] ], - [ "sw1:1b", "mux4:SEL", "green", [ "h0" ] ], - [ "mux2:OUT", "bargraph1:A2", "green", [ "v0" ] ], - [ "mux3:OUT", "bargraph1:A3", "green", [ "v0" ] ], - [ "mux4:OUT", "bargraph1:A4", "green", [ "v0" ] ], - [ "pwr7:VCC", "sw2:1a", "red", [ "v0" ] ], - [ "sw1:1a", "sw1:2a", "green", [ "h0" ] ], - [ "sw1:2a", "sw1:3a", "green", [ "h0" ] ], - [ "sw2:1a", "sw2:2a", "green", [ "h0" ] ], - [ "sw2:2a", "sw2:3a", "green", [ "h0" ] ], - [ "sw2:3a", "sw2:4a", "green", [ "h0" ] ], - [ "sw2:4a", "sw2:5a", "green", [ "h0" ] ], - [ "sw2:5a", "sw2:6a", "green", [ "h0" ] ], - [ "sw2:6a", "sw2:7a", "green", [ "h0" ] ], - [ "sw2:7a", "sw2:8a", "green", [ "h0" ] ], - [ "sw2:1b", "gate7:A", "green", [ "h0" ] ], - [ "sw2:2b", "gate7:B", "green", [ "h0" ] ], - [ "sw2:3b", "gate5:IN", "green", [ "h0" ] ], - [ "gate5:OUT", "gate4:B", "green", [ "v0" ] ], - [ "gate7:OUT", "gate4:A", "green", [ "v0" ] ], - [ "r1:2", "sw1:1b", "green", [ "h1.74", "v16.62" ] ], - [ "gnd7:GND", "r1:1", "black", [ "v0" ] ], - [ "r2:1", "gnd8:GND", "green", [ "h0" ] ], - [ "r4:1", "r3:1", "green", [ "h0" ] ], - [ "r3:1", "r2:1", "green", [ "h0" ] ], - [ - "gate1:A", - "clkgen1:CLK", - "green", - [ "h0", "v-48", "h-28.8", "v67.2", "h-57.6", "v38.4", "h-28.8", "v-57.6", "h28.8" ] - ], - [ "r2:2", "sw2:1b", "green", [ "h-9.6", "v17.8" ] ], - [ "r3:2", "sw2:2b", "green", [ "h-9.6", "v27.4" ] ], - [ "r4:2", "sw2:3b", "green", [ "h-9.6", "v27.4" ] ], - [ "bargraph1:A8", "gate4:OUT", "green", [ "h-37.9", "v305.65", "h-269.3" ] ] - ] -} \ No newline at end of file