| *SPEF "ieee 1481-1999" |
| *DESIGN "user_project_wrapper" |
| *DATE "11:11:11 Fri 11 11, 1111" |
| *VENDOR "OpenRCX" |
| *PROGRAM "Parallel Extraction" |
| *VERSION "1.0" |
| *DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE" |
| *DIVIDER / |
| *DELIMITER : |
| *BUS_DELIMITER [] |
| *T_UNIT 1 NS |
| *C_UNIT 1 PF |
| *R_UNIT 1 OHM |
| *L_UNIT 1 HENRY |
| |
| *NAME_MAP |
| *1 io_in[0] |
| *2 io_in[10] |
| *3 io_in[11] |
| *4 io_in[12] |
| *5 io_in[13] |
| *6 io_in[14] |
| *7 io_in[15] |
| *8 io_in[16] |
| *9 io_in[17] |
| *10 io_in[18] |
| *11 io_in[19] |
| *12 io_in[1] |
| *13 io_in[20] |
| *14 io_in[21] |
| *15 io_in[22] |
| *16 io_in[23] |
| *17 io_in[24] |
| *18 io_in[25] |
| *19 io_in[26] |
| *20 io_in[27] |
| *21 io_in[28] |
| *22 io_in[29] |
| *23 io_in[2] |
| *24 io_in[30] |
| *25 io_in[31] |
| *26 io_in[32] |
| *27 io_in[33] |
| *28 io_in[34] |
| *29 io_in[35] |
| *30 io_in[36] |
| *31 io_in[37] |
| *32 io_in[3] |
| *33 io_in[4] |
| *34 io_in[5] |
| *35 io_in[6] |
| *36 io_in[7] |
| *37 io_in[8] |
| *38 io_in[9] |
| *39 io_oeb[0] |
| *40 io_oeb[10] |
| *41 io_oeb[11] |
| *42 io_oeb[12] |
| *43 io_oeb[13] |
| *44 io_oeb[14] |
| *45 io_oeb[15] |
| *46 io_oeb[16] |
| *47 io_oeb[17] |
| *48 io_oeb[18] |
| *49 io_oeb[19] |
| *50 io_oeb[1] |
| *51 io_oeb[20] |
| *52 io_oeb[21] |
| *53 io_oeb[22] |
| *54 io_oeb[23] |
| *55 io_oeb[24] |
| *56 io_oeb[25] |
| *57 io_oeb[26] |
| *58 io_oeb[27] |
| *59 io_oeb[28] |
| *60 io_oeb[29] |
| *61 io_oeb[2] |
| *62 io_oeb[30] |
| *63 io_oeb[31] |
| *64 io_oeb[32] |
| *65 io_oeb[33] |
| *66 io_oeb[34] |
| *67 io_oeb[35] |
| *68 io_oeb[36] |
| *69 io_oeb[37] |
| *70 io_oeb[3] |
| *71 io_oeb[4] |
| *72 io_oeb[5] |
| *73 io_oeb[6] |
| *74 io_oeb[7] |
| *75 io_oeb[8] |
| *76 io_oeb[9] |
| *77 io_out[0] |
| *78 io_out[10] |
| *79 io_out[11] |
| *80 io_out[12] |
| *81 io_out[13] |
| *82 io_out[14] |
| *83 io_out[15] |
| *84 io_out[16] |
| *85 io_out[17] |
| *86 io_out[18] |
| *87 io_out[19] |
| *88 io_out[1] |
| *89 io_out[20] |
| *90 io_out[21] |
| *91 io_out[22] |
| *92 io_out[23] |
| *93 io_out[24] |
| *94 io_out[25] |
| *95 io_out[26] |
| *96 io_out[27] |
| *97 io_out[28] |
| *98 io_out[29] |
| *99 io_out[2] |
| *100 io_out[30] |
| *101 io_out[31] |
| *102 io_out[32] |
| *103 io_out[33] |
| *104 io_out[34] |
| *105 io_out[35] |
| *106 io_out[36] |
| *107 io_out[37] |
| *108 io_out[3] |
| *109 io_out[4] |
| *110 io_out[5] |
| *111 io_out[6] |
| *112 io_out[7] |
| *113 io_out[8] |
| *114 io_out[9] |
| *115 la_data_in[0] |
| *116 la_data_in[10] |
| *117 la_data_in[11] |
| *118 la_data_in[12] |
| *119 la_data_in[13] |
| *120 la_data_in[14] |
| *121 la_data_in[15] |
| *122 la_data_in[16] |
| *123 la_data_in[17] |
| *124 la_data_in[18] |
| *125 la_data_in[19] |
| *126 la_data_in[1] |
| *127 la_data_in[20] |
| *128 la_data_in[21] |
| *129 la_data_in[22] |
| *130 la_data_in[23] |
| *131 la_data_in[24] |
| *132 la_data_in[25] |
| *133 la_data_in[26] |
| *134 la_data_in[27] |
| *135 la_data_in[28] |
| *136 la_data_in[29] |
| *137 la_data_in[2] |
| *138 la_data_in[30] |
| *139 la_data_in[31] |
| *140 la_data_in[32] |
| *141 la_data_in[33] |
| *142 la_data_in[34] |
| *143 la_data_in[35] |
| *144 la_data_in[36] |
| *145 la_data_in[37] |
| *146 la_data_in[38] |
| *147 la_data_in[39] |
| *148 la_data_in[3] |
| *149 la_data_in[40] |
| *150 la_data_in[41] |
| *151 la_data_in[42] |
| *152 la_data_in[43] |
| *153 la_data_in[44] |
| *154 la_data_in[45] |
| *155 la_data_in[46] |
| *156 la_data_in[47] |
| *157 la_data_in[48] |
| *158 la_data_in[49] |
| *159 la_data_in[4] |
| *160 la_data_in[50] |
| *161 la_data_in[51] |
| *162 la_data_in[52] |
| *163 la_data_in[53] |
| *164 la_data_in[54] |
| *165 la_data_in[55] |
| *166 la_data_in[56] |
| *167 la_data_in[57] |
| *168 la_data_in[58] |
| *169 la_data_in[59] |
| *170 la_data_in[5] |
| *171 la_data_in[60] |
| *172 la_data_in[61] |
| *173 la_data_in[62] |
| *174 la_data_in[63] |
| *175 la_data_in[6] |
| *176 la_data_in[7] |
| *177 la_data_in[8] |
| *178 la_data_in[9] |
| *179 la_data_out[0] |
| *180 la_data_out[10] |
| *181 la_data_out[11] |
| *182 la_data_out[12] |
| *183 la_data_out[13] |
| *184 la_data_out[14] |
| *185 la_data_out[15] |
| *186 la_data_out[16] |
| *187 la_data_out[17] |
| *188 la_data_out[18] |
| *189 la_data_out[19] |
| *190 la_data_out[1] |
| *191 la_data_out[20] |
| *192 la_data_out[21] |
| *193 la_data_out[22] |
| *194 la_data_out[23] |
| *195 la_data_out[24] |
| *196 la_data_out[25] |
| *197 la_data_out[26] |
| *198 la_data_out[27] |
| *199 la_data_out[28] |
| *200 la_data_out[29] |
| *201 la_data_out[2] |
| *202 la_data_out[30] |
| *203 la_data_out[31] |
| *204 la_data_out[32] |
| *205 la_data_out[33] |
| *206 la_data_out[34] |
| *207 la_data_out[35] |
| *208 la_data_out[36] |
| *209 la_data_out[37] |
| *210 la_data_out[38] |
| *211 la_data_out[39] |
| *212 la_data_out[3] |
| *213 la_data_out[40] |
| *214 la_data_out[41] |
| *215 la_data_out[42] |
| *216 la_data_out[43] |
| *217 la_data_out[44] |
| *218 la_data_out[45] |
| *219 la_data_out[46] |
| *220 la_data_out[47] |
| *221 la_data_out[48] |
| *222 la_data_out[49] |
| *223 la_data_out[4] |
| *224 la_data_out[50] |
| *225 la_data_out[51] |
| *226 la_data_out[52] |
| *227 la_data_out[53] |
| *228 la_data_out[54] |
| *229 la_data_out[55] |
| *230 la_data_out[56] |
| *231 la_data_out[57] |
| *232 la_data_out[58] |
| *233 la_data_out[59] |
| *234 la_data_out[5] |
| *235 la_data_out[60] |
| *236 la_data_out[61] |
| *237 la_data_out[62] |
| *238 la_data_out[63] |
| *239 la_data_out[6] |
| *240 la_data_out[7] |
| *241 la_data_out[8] |
| *242 la_data_out[9] |
| *243 la_oenb[0] |
| *244 la_oenb[10] |
| *245 la_oenb[11] |
| *246 la_oenb[12] |
| *247 la_oenb[13] |
| *248 la_oenb[14] |
| *249 la_oenb[15] |
| *250 la_oenb[16] |
| *251 la_oenb[17] |
| *252 la_oenb[18] |
| *253 la_oenb[19] |
| *254 la_oenb[1] |
| *255 la_oenb[20] |
| *256 la_oenb[21] |
| *257 la_oenb[22] |
| *258 la_oenb[23] |
| *259 la_oenb[24] |
| *260 la_oenb[25] |
| *261 la_oenb[26] |
| *262 la_oenb[27] |
| *263 la_oenb[28] |
| *264 la_oenb[29] |
| *265 la_oenb[2] |
| *266 la_oenb[30] |
| *267 la_oenb[31] |
| *268 la_oenb[32] |
| *269 la_oenb[33] |
| *270 la_oenb[34] |
| *271 la_oenb[35] |
| *272 la_oenb[36] |
| *273 la_oenb[37] |
| *274 la_oenb[38] |
| *275 la_oenb[39] |
| *276 la_oenb[3] |
| *277 la_oenb[40] |
| *278 la_oenb[41] |
| *279 la_oenb[42] |
| *280 la_oenb[43] |
| *281 la_oenb[44] |
| *282 la_oenb[45] |
| *283 la_oenb[46] |
| *284 la_oenb[47] |
| *285 la_oenb[48] |
| *286 la_oenb[49] |
| *287 la_oenb[4] |
| *288 la_oenb[50] |
| *289 la_oenb[51] |
| *290 la_oenb[52] |
| *291 la_oenb[53] |
| *292 la_oenb[54] |
| *293 la_oenb[55] |
| *294 la_oenb[56] |
| *295 la_oenb[57] |
| *296 la_oenb[58] |
| *297 la_oenb[59] |
| *298 la_oenb[5] |
| *299 la_oenb[60] |
| *300 la_oenb[61] |
| *301 la_oenb[62] |
| *302 la_oenb[63] |
| *303 la_oenb[6] |
| *304 la_oenb[7] |
| *305 la_oenb[8] |
| *306 la_oenb[9] |
| *307 user_clock2 |
| *308 user_irq[0] |
| *309 user_irq[1] |
| *310 user_irq[2] |
| *313 wb_clk_i |
| *314 wb_rst_i |
| *315 wbs_ack_o |
| *316 wbs_adr_i[0] |
| *317 wbs_adr_i[10] |
| *318 wbs_adr_i[11] |
| *319 wbs_adr_i[12] |
| *320 wbs_adr_i[13] |
| *321 wbs_adr_i[14] |
| *322 wbs_adr_i[15] |
| *323 wbs_adr_i[16] |
| *324 wbs_adr_i[17] |
| *325 wbs_adr_i[18] |
| *326 wbs_adr_i[19] |
| *327 wbs_adr_i[1] |
| *328 wbs_adr_i[20] |
| *329 wbs_adr_i[21] |
| *330 wbs_adr_i[22] |
| *331 wbs_adr_i[23] |
| *332 wbs_adr_i[24] |
| *333 wbs_adr_i[25] |
| *334 wbs_adr_i[26] |
| *335 wbs_adr_i[27] |
| *336 wbs_adr_i[28] |
| *337 wbs_adr_i[29] |
| *338 wbs_adr_i[2] |
| *339 wbs_adr_i[30] |
| *340 wbs_adr_i[31] |
| *341 wbs_adr_i[3] |
| *342 wbs_adr_i[4] |
| *343 wbs_adr_i[5] |
| *344 wbs_adr_i[6] |
| *345 wbs_adr_i[7] |
| *346 wbs_adr_i[8] |
| *347 wbs_adr_i[9] |
| *348 wbs_cyc_i |
| *349 wbs_dat_i[0] |
| *350 wbs_dat_i[10] |
| *351 wbs_dat_i[11] |
| *352 wbs_dat_i[12] |
| *353 wbs_dat_i[13] |
| *354 wbs_dat_i[14] |
| *355 wbs_dat_i[15] |
| *356 wbs_dat_i[16] |
| *357 wbs_dat_i[17] |
| *358 wbs_dat_i[18] |
| *359 wbs_dat_i[19] |
| *360 wbs_dat_i[1] |
| *361 wbs_dat_i[20] |
| *362 wbs_dat_i[21] |
| *363 wbs_dat_i[22] |
| *364 wbs_dat_i[23] |
| *365 wbs_dat_i[24] |
| *366 wbs_dat_i[25] |
| *367 wbs_dat_i[26] |
| *368 wbs_dat_i[27] |
| *369 wbs_dat_i[28] |
| *370 wbs_dat_i[29] |
| *371 wbs_dat_i[2] |
| *372 wbs_dat_i[30] |
| *373 wbs_dat_i[31] |
| *374 wbs_dat_i[3] |
| *375 wbs_dat_i[4] |
| *376 wbs_dat_i[5] |
| *377 wbs_dat_i[6] |
| *378 wbs_dat_i[7] |
| *379 wbs_dat_i[8] |
| *380 wbs_dat_i[9] |
| *381 wbs_dat_o[0] |
| *382 wbs_dat_o[10] |
| *383 wbs_dat_o[11] |
| *384 wbs_dat_o[12] |
| *385 wbs_dat_o[13] |
| *386 wbs_dat_o[14] |
| *387 wbs_dat_o[15] |
| *388 wbs_dat_o[16] |
| *389 wbs_dat_o[17] |
| *390 wbs_dat_o[18] |
| *391 wbs_dat_o[19] |
| *392 wbs_dat_o[1] |
| *393 wbs_dat_o[20] |
| *394 wbs_dat_o[21] |
| *395 wbs_dat_o[22] |
| *396 wbs_dat_o[23] |
| *397 wbs_dat_o[24] |
| *398 wbs_dat_o[25] |
| *399 wbs_dat_o[26] |
| *400 wbs_dat_o[27] |
| *401 wbs_dat_o[28] |
| *402 wbs_dat_o[29] |
| *403 wbs_dat_o[2] |
| *404 wbs_dat_o[30] |
| *405 wbs_dat_o[31] |
| *406 wbs_dat_o[3] |
| *407 wbs_dat_o[4] |
| *408 wbs_dat_o[5] |
| *409 wbs_dat_o[6] |
| *410 wbs_dat_o[7] |
| *411 wbs_dat_o[8] |
| *412 wbs_dat_o[9] |
| *413 wbs_sel_i[0] |
| *414 wbs_sel_i[1] |
| *415 wbs_sel_i[2] |
| *416 wbs_sel_i[3] |
| *417 wbs_stb_i |
| *418 wbs_we_i |
| *419 wrapped_vga_clock |
| |
| *PORTS |
| io_in[0] I |
| io_in[10] I |
| io_in[11] I |
| io_in[12] I |
| io_in[13] I |
| io_in[14] I |
| io_in[15] I |
| io_in[16] I |
| io_in[17] I |
| io_in[18] I |
| io_in[19] I |
| io_in[1] I |
| io_in[20] I |
| io_in[21] I |
| io_in[22] I |
| io_in[23] I |
| io_in[24] I |
| io_in[25] I |
| io_in[26] I |
| io_in[27] I |
| io_in[28] I |
| io_in[29] I |
| io_in[2] I |
| io_in[30] I |
| io_in[31] I |
| io_in[32] I |
| io_in[33] I |
| io_in[34] I |
| io_in[35] I |
| io_in[36] I |
| io_in[37] I |
| io_in[3] I |
| io_in[4] I |
| io_in[5] I |
| io_in[6] I |
| io_in[7] I |
| io_in[8] I |
| io_in[9] I |
| io_oeb[0] O |
| io_oeb[10] O |
| io_oeb[11] O |
| io_oeb[12] O |
| io_oeb[13] O |
| io_oeb[14] O |
| io_oeb[15] O |
| io_oeb[16] O |
| io_oeb[17] O |
| io_oeb[18] O |
| io_oeb[19] O |
| io_oeb[1] O |
| io_oeb[20] O |
| io_oeb[21] O |
| io_oeb[22] O |
| io_oeb[23] O |
| io_oeb[24] O |
| io_oeb[25] O |
| io_oeb[26] O |
| io_oeb[27] O |
| io_oeb[28] O |
| io_oeb[29] O |
| io_oeb[2] O |
| io_oeb[30] O |
| io_oeb[31] O |
| io_oeb[32] O |
| io_oeb[33] O |
| io_oeb[34] O |
| io_oeb[35] O |
| io_oeb[36] O |
| io_oeb[37] O |
| io_oeb[3] O |
| io_oeb[4] O |
| io_oeb[5] O |
| io_oeb[6] O |
| io_oeb[7] O |
| io_oeb[8] O |
| io_oeb[9] O |
| io_out[0] O |
| io_out[10] O |
| io_out[11] O |
| io_out[12] O |
| io_out[13] O |
| io_out[14] O |
| io_out[15] O |
| io_out[16] O |
| io_out[17] O |
| io_out[18] O |
| io_out[19] O |
| io_out[1] O |
| io_out[20] O |
| io_out[21] O |
| io_out[22] O |
| io_out[23] O |
| io_out[24] O |
| io_out[25] O |
| io_out[26] O |
| io_out[27] O |
| io_out[28] O |
| io_out[29] O |
| io_out[2] O |
| io_out[30] O |
| io_out[31] O |
| io_out[32] O |
| io_out[33] O |
| io_out[34] O |
| io_out[35] O |
| io_out[36] O |
| io_out[37] O |
| io_out[3] O |
| io_out[4] O |
| io_out[5] O |
| io_out[6] O |
| io_out[7] O |
| io_out[8] O |
| io_out[9] O |
| la_data_in[0] I |
| la_data_in[10] I |
| la_data_in[11] I |
| la_data_in[12] I |
| la_data_in[13] I |
| la_data_in[14] I |
| la_data_in[15] I |
| la_data_in[16] I |
| la_data_in[17] I |
| la_data_in[18] I |
| la_data_in[19] I |
| la_data_in[1] I |
| la_data_in[20] I |
| la_data_in[21] I |
| la_data_in[22] I |
| la_data_in[23] I |
| la_data_in[24] I |
| la_data_in[25] I |
| la_data_in[26] I |
| la_data_in[27] I |
| la_data_in[28] I |
| la_data_in[29] I |
| la_data_in[2] I |
| la_data_in[30] I |
| la_data_in[31] I |
| la_data_in[32] I |
| la_data_in[33] I |
| la_data_in[34] I |
| la_data_in[35] I |
| la_data_in[36] I |
| la_data_in[37] I |
| la_data_in[38] I |
| la_data_in[39] I |
| la_data_in[3] I |
| la_data_in[40] I |
| la_data_in[41] I |
| la_data_in[42] I |
| la_data_in[43] I |
| la_data_in[44] I |
| la_data_in[45] I |
| la_data_in[46] I |
| la_data_in[47] I |
| la_data_in[48] I |
| la_data_in[49] I |
| la_data_in[4] I |
| la_data_in[50] I |
| la_data_in[51] I |
| la_data_in[52] I |
| la_data_in[53] I |
| la_data_in[54] I |
| la_data_in[55] I |
| la_data_in[56] I |
| la_data_in[57] I |
| la_data_in[58] I |
| la_data_in[59] I |
| la_data_in[5] I |
| la_data_in[60] I |
| la_data_in[61] I |
| la_data_in[62] I |
| la_data_in[63] I |
| la_data_in[6] I |
| la_data_in[7] I |
| la_data_in[8] I |
| la_data_in[9] I |
| la_data_out[0] O |
| la_data_out[10] O |
| la_data_out[11] O |
| la_data_out[12] O |
| la_data_out[13] O |
| la_data_out[14] O |
| la_data_out[15] O |
| la_data_out[16] O |
| la_data_out[17] O |
| la_data_out[18] O |
| la_data_out[19] O |
| la_data_out[1] O |
| la_data_out[20] O |
| la_data_out[21] O |
| la_data_out[22] O |
| la_data_out[23] O |
| la_data_out[24] O |
| la_data_out[25] O |
| la_data_out[26] O |
| la_data_out[27] O |
| la_data_out[28] O |
| la_data_out[29] O |
| la_data_out[2] O |
| la_data_out[30] O |
| la_data_out[31] O |
| la_data_out[32] O |
| la_data_out[33] O |
| la_data_out[34] O |
| la_data_out[35] O |
| la_data_out[36] O |
| la_data_out[37] O |
| la_data_out[38] O |
| la_data_out[39] O |
| la_data_out[3] O |
| la_data_out[40] O |
| la_data_out[41] O |
| la_data_out[42] O |
| la_data_out[43] O |
| la_data_out[44] O |
| la_data_out[45] O |
| la_data_out[46] O |
| la_data_out[47] O |
| la_data_out[48] O |
| la_data_out[49] O |
| la_data_out[4] O |
| la_data_out[50] O |
| la_data_out[51] O |
| la_data_out[52] O |
| la_data_out[53] O |
| la_data_out[54] O |
| la_data_out[55] O |
| la_data_out[56] O |
| la_data_out[57] O |
| la_data_out[58] O |
| la_data_out[59] O |
| la_data_out[5] O |
| la_data_out[60] O |
| la_data_out[61] O |
| la_data_out[62] O |
| la_data_out[63] O |
| la_data_out[6] O |
| la_data_out[7] O |
| la_data_out[8] O |
| la_data_out[9] O |
| la_oenb[0] I |
| la_oenb[10] I |
| la_oenb[11] I |
| la_oenb[12] I |
| la_oenb[13] I |
| la_oenb[14] I |
| la_oenb[15] I |
| la_oenb[16] I |
| la_oenb[17] I |
| la_oenb[18] I |
| la_oenb[19] I |
| la_oenb[1] I |
| la_oenb[20] I |
| la_oenb[21] I |
| la_oenb[22] I |
| la_oenb[23] I |
| la_oenb[24] I |
| la_oenb[25] I |
| la_oenb[26] I |
| la_oenb[27] I |
| la_oenb[28] I |
| la_oenb[29] I |
| la_oenb[2] I |
| la_oenb[30] I |
| la_oenb[31] I |
| la_oenb[32] I |
| la_oenb[33] I |
| la_oenb[34] I |
| la_oenb[35] I |
| la_oenb[36] I |
| la_oenb[37] I |
| la_oenb[38] I |
| la_oenb[39] I |
| la_oenb[3] I |
| la_oenb[40] I |
| la_oenb[41] I |
| la_oenb[42] I |
| la_oenb[43] I |
| la_oenb[44] I |
| la_oenb[45] I |
| la_oenb[46] I |
| la_oenb[47] I |
| la_oenb[48] I |
| la_oenb[49] I |
| la_oenb[4] I |
| la_oenb[50] I |
| la_oenb[51] I |
| la_oenb[52] I |
| la_oenb[53] I |
| la_oenb[54] I |
| la_oenb[55] I |
| la_oenb[56] I |
| la_oenb[57] I |
| la_oenb[58] I |
| la_oenb[59] I |
| la_oenb[5] I |
| la_oenb[60] I |
| la_oenb[61] I |
| la_oenb[62] I |
| la_oenb[63] I |
| la_oenb[6] I |
| la_oenb[7] I |
| la_oenb[8] I |
| la_oenb[9] I |
| user_clock2 I |
| user_irq[0] O |
| user_irq[1] O |
| user_irq[2] O |
| wb_clk_i I |
| wb_rst_i I |
| wbs_ack_o O |
| wbs_adr_i[0] I |
| wbs_adr_i[10] I |
| wbs_adr_i[11] I |
| wbs_adr_i[12] I |
| wbs_adr_i[13] I |
| wbs_adr_i[14] I |
| wbs_adr_i[15] I |
| wbs_adr_i[16] I |
| wbs_adr_i[17] I |
| wbs_adr_i[18] I |
| wbs_adr_i[19] I |
| wbs_adr_i[1] I |
| wbs_adr_i[20] I |
| wbs_adr_i[21] I |
| wbs_adr_i[22] I |
| wbs_adr_i[23] I |
| wbs_adr_i[24] I |
| wbs_adr_i[25] I |
| wbs_adr_i[26] I |
| wbs_adr_i[27] I |
| wbs_adr_i[28] I |
| wbs_adr_i[29] I |
| wbs_adr_i[2] I |
| wbs_adr_i[30] I |
| wbs_adr_i[31] I |
| wbs_adr_i[3] I |
| wbs_adr_i[4] I |
| wbs_adr_i[5] I |
| wbs_adr_i[6] I |
| wbs_adr_i[7] I |
| wbs_adr_i[8] I |
| wbs_adr_i[9] I |
| wbs_cyc_i I |
| wbs_dat_i[0] I |
| wbs_dat_i[10] I |
| wbs_dat_i[11] I |
| wbs_dat_i[12] I |
| wbs_dat_i[13] I |
| wbs_dat_i[14] I |
| wbs_dat_i[15] I |
| wbs_dat_i[16] I |
| wbs_dat_i[17] I |
| wbs_dat_i[18] I |
| wbs_dat_i[19] I |
| wbs_dat_i[1] I |
| wbs_dat_i[20] I |
| wbs_dat_i[21] I |
| wbs_dat_i[22] I |
| wbs_dat_i[23] I |
| wbs_dat_i[24] I |
| wbs_dat_i[25] I |
| wbs_dat_i[26] I |
| wbs_dat_i[27] I |
| wbs_dat_i[28] I |
| wbs_dat_i[29] I |
| wbs_dat_i[2] I |
| wbs_dat_i[30] I |
| wbs_dat_i[31] I |
| wbs_dat_i[3] I |
| wbs_dat_i[4] I |
| wbs_dat_i[5] I |
| wbs_dat_i[6] I |
| wbs_dat_i[7] I |
| wbs_dat_i[8] I |
| wbs_dat_i[9] I |
| wbs_dat_o[0] O |
| wbs_dat_o[10] O |
| wbs_dat_o[11] O |
| wbs_dat_o[12] O |
| wbs_dat_o[13] O |
| wbs_dat_o[14] O |
| wbs_dat_o[15] O |
| wbs_dat_o[16] O |
| wbs_dat_o[17] O |
| wbs_dat_o[18] O |
| wbs_dat_o[19] O |
| wbs_dat_o[1] O |
| wbs_dat_o[20] O |
| wbs_dat_o[21] O |
| wbs_dat_o[22] O |
| wbs_dat_o[23] O |
| wbs_dat_o[24] O |
| wbs_dat_o[25] O |
| wbs_dat_o[26] O |
| wbs_dat_o[27] O |
| wbs_dat_o[28] O |
| wbs_dat_o[29] O |
| wbs_dat_o[2] O |
| wbs_dat_o[30] O |
| wbs_dat_o[31] O |
| wbs_dat_o[3] O |
| wbs_dat_o[4] O |
| wbs_dat_o[5] O |
| wbs_dat_o[6] O |
| wbs_dat_o[7] O |
| wbs_dat_o[8] O |
| wbs_dat_o[9] O |
| wbs_sel_i[0] I |
| wbs_sel_i[1] I |
| wbs_sel_i[2] I |
| wbs_sel_i[3] I |
| wbs_stb_i I |
| wbs_we_i I |
| |
| *D_NET *1 0.286099 |
| *CONN |
| *P io_in[0] I |
| *I *419:io_in[0] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[0] 0.00466579 |
| 2 *419:io_in[0] 0.0011599 |
| 3 *1:12 0.086614 |
| 4 *1:11 0.0854541 |
| 5 *1:9 0.0517698 |
| 6 *1:7 0.0564356 |
| 7 *1:12 *30:12 0 |
| 8 *1:12 *66:11 0 |
| *RES |
| 1 io_in[0] *1:7 37.305 |
| 2 *1:7 *1:9 406.44 |
| 3 *1:9 *1:11 4.5 |
| 4 *1:11 *1:12 655.65 |
| 5 *1:12 *419:io_in[0] 22.32 |
| *END |
| |
| *D_NET *2 0.214119 |
| *CONN |
| *P io_in[10] I |
| *I *419:io_in[10] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[10] 0.00468295 |
| 2 *419:io_in[10] 0.00023698 |
| 3 *2:17 0.00551597 |
| 4 *2:12 0.015211 |
| 5 *2:11 0.00993204 |
| 6 *2:9 0.0303161 |
| 7 *2:7 0.034999 |
| 8 *2:9 *41:10 0.113225 |
| *RES |
| 1 io_in[10] *2:7 37.305 |
| 2 *2:7 *2:9 374.04 |
| 3 *2:9 *2:11 4.5 |
| 4 *2:11 *2:12 75.69 |
| 5 *2:12 *2:17 49.41 |
| 6 *2:17 *419:io_in[10] 6.48 |
| *END |
| |
| *D_NET *3 0.182701 |
| *CONN |
| *P io_in[11] I |
| *I *419:io_in[11] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[11] 0.000363112 |
| 2 *419:io_in[11] 0.00268609 |
| 3 *3:19 0.0195899 |
| 4 *3:18 0.0195776 |
| 5 *3:13 0.0713973 |
| 6 *3:11 0.0690866 |
| 7 *3:19 io_oeb[10] 0 |
| *RES |
| 1 io_in[11] *3:11 3.195 |
| 2 *3:11 *3:13 434.97 |
| 3 *3:13 *3:18 29.43 |
| 4 *3:18 *3:19 131.85 |
| 5 *3:19 *419:io_in[11] 32.22 |
| *END |
| |
| *D_NET *4 0.350264 |
| *CONN |
| *P io_in[12] I |
| *I *419:io_in[12] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[12] 0.00100991 |
| 2 *419:io_in[12] 0.000789542 |
| 3 *4:14 0.00191576 |
| 4 *4:13 0.00112622 |
| 5 *4:11 0.0455873 |
| 6 *4:10 0.0455873 |
| 7 *4:8 0.0126576 |
| 8 *4:7 0.0136675 |
| 9 *4:11 *419:io_in[13] 0 |
| 10 *4:11 *419:io_in[27] 0 |
| 11 *4:11 *8:16 0.181298 |
| 12 *4:11 *52:11 0.000893611 |
| 13 *4:14 io_out[20] 0.0255963 |
| 14 *4:14 *7:11 0.0201347 |
| *RES |
| 1 io_in[12] *4:7 12.825 |
| 2 *4:7 *4:8 97.11 |
| 3 *4:8 *4:10 4.5 |
| 4 *4:10 *4:11 576.63 |
| 5 *4:11 *4:13 4.5 |
| 6 *4:13 *4:14 65.61 |
| 7 *4:14 *419:io_in[12] 10.125 |
| *END |
| |
| *D_NET *5 0.206221 |
| *CONN |
| *P io_in[13] I |
| *I *419:io_in[13] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[13] 0.0572589 |
| 2 *419:io_in[13] 0.00339116 |
| 3 *5:8 0.0140084 |
| 4 *5:7 0.0106173 |
| 5 *5:5 0.0572589 |
| 6 *5:8 *13:17 0 |
| 7 *5:8 *17:16 0.0636867 |
| 8 *4:11 *419:io_in[13] 0 |
| *RES |
| 1 io_in[13] *5:5 448.245 |
| 2 *5:5 *5:7 4.5 |
| 3 *5:7 *5:8 162.09 |
| 4 *5:8 *419:io_in[13] 41.49 |
| *END |
| |
| *D_NET *6 0.190362 |
| *CONN |
| *P io_in[14] I |
| *I *419:io_in[14] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[14] 0.000264341 |
| 2 *419:io_in[14] 0.00161237 |
| 3 *6:19 0.00626593 |
| 4 *6:16 0.0332366 |
| 5 *6:15 0.0285831 |
| 6 *6:13 0.0565876 |
| 7 *6:11 0.056852 |
| 8 *6:16 *11:13 0 |
| 9 *6:19 *9:14 0.00696013 |
| *RES |
| 1 io_in[14] *6:11 2.655 |
| 2 *6:11 *6:13 443.07 |
| 3 *6:13 *6:15 4.5 |
| 4 *6:15 *6:16 220.23 |
| 5 *6:16 *6:19 48.33 |
| 6 *6:19 *419:io_in[14] 24.12 |
| *END |
| |
| *D_NET *7 0.288994 |
| *CONN |
| *P io_in[15] I |
| *I *419:io_in[15] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[15] 0.03691 |
| 2 *419:io_in[15] 0.000828272 |
| 3 *7:11 0.00435145 |
| 4 *7:10 0.00352317 |
| 5 *7:8 0.0604975 |
| 6 *7:7 0.0604975 |
| 7 *7:5 0.03691 |
| 8 *7:8 *11:16 0.0538724 |
| 9 *7:8 *32:11 0.00465589 |
| 10 *7:8 *37:11 0.00592003 |
| 11 *7:8 *38:19 5.34641e-05 |
| 12 *7:8 *61:11 0 |
| 13 *7:8 *98:9 0.000839793 |
| 14 *7:8 *100:11 0 |
| 15 *7:8 *110:11 0 |
| 16 *7:8 *111:11 0 |
| 17 *4:14 *7:11 0.0201347 |
| *RES |
| 1 io_in[15] *7:5 283.725 |
| 2 *7:5 *7:7 4.5 |
| 3 *7:7 *7:8 567.45 |
| 4 *7:8 *7:10 4.5 |
| 5 *7:10 *7:11 51.57 |
| 6 *7:11 *419:io_in[15] 10.305 |
| *END |
| |
| *D_NET *8 0.392126 |
| *CONN |
| *P io_in[16] I |
| *I *419:io_in[16] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[16] 0.000247817 |
| 2 *419:io_in[16] 0.000121656 |
| 3 *8:19 0.00796154 |
| 4 *8:18 0.00783988 |
| 5 *8:16 0.0260383 |
| 6 *8:15 0.0260383 |
| 7 *8:13 0.0361714 |
| 8 *8:11 0.0364192 |
| 9 *8:13 *41:13 0 |
| 10 *8:16 *52:11 0.0263641 |
| 11 *8:19 *11:19 0.0425678 |
| 12 *8:19 *87:8 0.000913148 |
| 13 *8:19 *88:14 0.00014428 |
| 14 *4:11 *8:16 0.181298 |
| *RES |
| 1 io_in[16] *8:11 2.655 |
| 2 *8:11 *8:13 278.19 |
| 3 *8:13 *8:15 4.5 |
| 4 *8:15 *8:16 454.41 |
| 5 *8:16 *8:18 4.5 |
| 6 *8:18 *8:19 114.39 |
| 7 *8:19 *419:io_in[16] 5.265 |
| *END |
| |
| *D_NET *9 0.177805 |
| *CONN |
| *P io_in[17] I |
| *I *419:io_in[17] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[17] 0.00141746 |
| 2 *419:io_in[17] 0.00169029 |
| 3 *9:14 0.0436689 |
| 4 *9:13 0.0419786 |
| 5 *9:11 0.0346506 |
| 6 *9:10 0.0360681 |
| 7 *9:14 *48:16 0.0032737 |
| 8 *9:14 *92:11 0.00166699 |
| 9 *9:14 *93:11 0.00643036 |
| 10 *6:19 *9:14 0.00696013 |
| *RES |
| 1 io_in[17] *9:10 19.935 |
| 2 *9:10 *9:11 266.49 |
| 3 *9:11 *9:13 4.5 |
| 4 *9:13 *9:14 303.03 |
| 5 *9:14 *419:io_in[17] 24.48 |
| *END |
| |
| *D_NET *10 0.206073 |
| *CONN |
| *P io_in[18] I |
| *I *419:io_in[18] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[18] 0.00107486 |
| 2 *419:io_in[18] 0.000334403 |
| 3 *10:14 0.0092803 |
| 4 *10:13 0.00894589 |
| 5 *10:11 0.0532841 |
| 6 *10:10 0.0532841 |
| 7 *10:8 0.00747897 |
| 8 *10:7 0.00855383 |
| 9 *10:8 *86:14 0.0175012 |
| 10 *10:14 *22:19 0.00419659 |
| 11 *10:14 *44:8 0.0421392 |
| 12 *10:14 *53:8 0 |
| 13 *10:14 *84:8 0 |
| 14 *10:14 *113:14 0 |
| *RES |
| 1 io_in[18] *10:7 12.825 |
| 2 *10:7 *10:8 79.29 |
| 3 *10:8 *10:10 4.5 |
| 4 *10:10 *10:11 407.43 |
| 5 *10:11 *10:13 4.5 |
| 6 *10:13 *10:14 128.97 |
| 7 *10:14 *419:io_in[18] 6.525 |
| *END |
| |
| *D_NET *11 0.232557 |
| *CONN |
| *P io_in[19] I |
| *I *419:io_in[19] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[19] 0.000178873 |
| 2 *419:io_in[19] 8.29261e-05 |
| 3 *11:19 0.00110373 |
| 4 *11:18 0.0010208 |
| 5 *11:16 0.00929913 |
| 6 *11:15 0.00929913 |
| 7 *11:13 0.0368922 |
| 8 *11:11 0.0370711 |
| 9 *11:16 *61:11 0 |
| 10 *11:16 *100:11 0 |
| 11 *11:16 *110:11 0 |
| 12 *11:19 *87:8 0.0408818 |
| 13 *11:19 *88:14 0.000286996 |
| 14 *6:16 *11:13 0 |
| 15 *7:8 *11:16 0.0538724 |
| 16 *8:19 *11:19 0.0425678 |
| *RES |
| 1 io_in[19] *11:11 2.115 |
| 2 *11:11 *11:13 283.59 |
| 3 *11:13 *11:15 4.5 |
| 4 *11:15 *11:16 135.63 |
| 5 *11:16 *11:18 4.5 |
| 6 *11:18 *11:19 113.31 |
| 7 *11:19 *419:io_in[19] 5.085 |
| *END |
| |
| *D_NET *12 0.268897 |
| *CONN |
| *P io_in[1] I |
| *I *419:io_in[1] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[1] 0.000370905 |
| 2 *419:io_in[1] 0.000304304 |
| 3 *12:19 0.0154483 |
| 4 *12:18 0.015144 |
| 5 *12:16 0.0760461 |
| 6 *12:15 0.0760461 |
| 7 *12:13 0.0425829 |
| 8 *12:11 0.0429538 |
| *RES |
| 1 io_in[1] *12:11 3.195 |
| 2 *12:11 *12:13 335.07 |
| 3 *12:13 *12:15 4.5 |
| 4 *12:15 *12:16 583.29 |
| 5 *12:16 *12:18 4.5 |
| 6 *12:18 *12:19 116.01 |
| 7 *12:19 *419:io_in[1] 11.52 |
| *END |
| |
| *D_NET *13 0.19125 |
| *CONN |
| *P io_in[20] I |
| *I *419:io_in[20] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[20] 0.00180027 |
| 2 *419:io_in[20] 0.00144 |
| 3 *13:17 0.0118314 |
| 4 *13:16 0.0103914 |
| 5 *13:14 0.00642837 |
| 6 *13:13 0.00642837 |
| 7 *13:11 0.0345544 |
| 8 *13:10 0.0363547 |
| 9 *419:io_in[20] *68:11 0.00172419 |
| 10 *419:io_in[20] *101:16 0.00509955 |
| 11 *13:10 *87:11 0 |
| 12 *13:14 *43:11 0.0382789 |
| 13 *13:17 *17:16 0 |
| 14 *13:17 *55:11 0.0369186 |
| 15 *5:8 *13:17 0 |
| *RES |
| 1 io_in[20] *13:10 22.455 |
| 2 *13:10 *13:11 265.77 |
| 3 *13:11 *13:13 4.5 |
| 4 *13:13 *13:14 96.03 |
| 5 *13:14 *13:16 4.5 |
| 6 *13:16 *13:17 123.12 |
| 7 *13:17 *419:io_in[20] 32.85 |
| *END |
| |
| *D_NET *14 0.123045 |
| *CONN |
| *P io_in[21] I |
| *I *419:io_in[21] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[21] 0.00135201 |
| 2 *419:io_in[21] 0.00238932 |
| 3 *14:14 0.0260756 |
| 4 *14:13 0.0236863 |
| 5 *14:11 0.0339676 |
| 6 *14:10 0.0353196 |
| 7 *14:10 *54:14 0.000254726 |
| *RES |
| 1 io_in[21] *14:10 19.935 |
| 2 *14:10 *14:11 261.45 |
| 3 *14:11 *14:13 4.5 |
| 4 *14:13 *14:14 184.23 |
| 5 *14:14 *419:io_in[21] 29.52 |
| *END |
| |
| *D_NET *15 0.133849 |
| *CONN |
| *P io_in[22] I |
| *I *419:io_in[22] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[22] 0.00483482 |
| 2 *419:io_in[22] 0.00129814 |
| 3 *15:17 0.0057742 |
| 4 *15:12 0.0212594 |
| 5 *15:11 0.0167833 |
| 6 *15:9 0.0332768 |
| 7 *15:7 0.0381116 |
| 8 *15:12 *102:5 0.0125111 |
| *RES |
| 1 io_in[22] *15:7 37.305 |
| 2 *15:7 *15:9 255.24 |
| 3 *15:9 *15:11 4.5 |
| 4 *15:11 *15:12 174.15 |
| 5 *15:12 *15:17 42.75 |
| 6 *15:17 *419:io_in[22] 9.585 |
| *END |
| |
| *D_NET *16 0.153615 |
| *CONN |
| *P io_in[23] I |
| *I *419:io_in[23] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[23] 0.000345489 |
| 2 *419:io_in[23] 0.0374707 |
| 3 *16:15 0.0374707 |
| 4 *16:13 0.0389915 |
| 5 *16:11 0.039337 |
| *RES |
| 1 io_in[23] *16:11 3.195 |
| 2 *16:11 *16:13 299.61 |
| 3 *16:13 *16:15 4.5 |
| 4 *16:15 *419:io_in[23] 291.645 |
| *END |
| |
| *D_NET *17 0.300846 |
| *CONN |
| *P io_in[24] I |
| *I *419:io_in[24] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[24] 0.000201168 |
| 2 *419:io_in[24] 0 |
| 3 *17:28 0.00237128 |
| 4 *17:16 0.0339303 |
| 5 *17:15 0.031559 |
| 6 *17:13 0.0803158 |
| 7 *17:11 0.080517 |
| 8 *17:16 *419:io_in[28] 0.000266183 |
| 9 *17:16 *57:11 0 |
| 10 *17:16 *107:11 0 |
| 11 *17:28 *55:11 0.0079988 |
| 12 *5:8 *17:16 0.0636867 |
| 13 *13:17 *17:16 0 |
| *RES |
| 1 io_in[24] *17:11 1.935 |
| 2 *17:11 *17:13 508.41 |
| 3 *17:13 *17:15 4.5 |
| 4 *17:15 *17:16 321.57 |
| 5 *17:16 *17:28 45.54 |
| 6 *17:28 *419:io_in[24] 4.5 |
| *END |
| |
| *D_NET *18 0.203196 |
| *CONN |
| *P io_in[25] I |
| *I *419:io_in[25] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[25] 0.000125876 |
| 2 *419:io_in[25] 0.00508018 |
| 3 *18:16 0.0467957 |
| 4 *18:15 0.0417155 |
| 5 *18:13 0.0546762 |
| 6 *18:11 0.0548021 |
| *RES |
| 1 io_in[25] *18:11 1.395 |
| 2 *18:11 *18:13 346.41 |
| 3 *18:13 *18:15 4.5 |
| 4 *18:15 *18:16 318.69 |
| 5 *18:16 *419:io_in[25] 35.685 |
| *END |
| |
| *D_NET *19 0.135203 |
| *CONN |
| *P io_in[26] I |
| *I *419:io_in[26] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[26] 0.00179421 |
| 2 *419:io_in[26] 0.00386758 |
| 3 *19:12 0.0229351 |
| 4 *19:11 0.0190675 |
| 5 *19:9 0.0428721 |
| 6 *19:7 0.0446663 |
| *RES |
| 1 io_in[26] *19:7 13.185 |
| 2 *19:7 *19:9 336.24 |
| 3 *19:9 *19:11 4.5 |
| 4 *19:11 *19:12 145.35 |
| 5 *19:12 *419:io_in[26] 32.985 |
| *END |
| |
| *D_NET *20 0.131466 |
| *CONN |
| *P io_in[27] I |
| *I *419:io_in[27] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[27] 0.00035683 |
| 2 *419:io_in[27] 0.00164616 |
| 3 *20:16 0.00953959 |
| 4 *20:15 0.00789343 |
| 5 *20:13 0.0558366 |
| 6 *20:11 0.0561935 |
| 7 *419:io_in[27] *97:11 0 |
| 8 *4:11 *419:io_in[27] 0 |
| *RES |
| 1 io_in[27] *20:11 3.015 |
| 2 *20:11 *20:13 435.51 |
| 3 *20:13 *20:15 4.5 |
| 4 *20:15 *20:16 59.67 |
| 5 *20:16 *419:io_in[27] 27.81 |
| *END |
| |
| *D_NET *21 0.170759 |
| *CONN |
| *P io_in[28] I |
| *I *419:io_in[28] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[28] 0.0312392 |
| 2 *419:io_in[28] 0.00137473 |
| 3 *21:9 0.0112687 |
| 4 *21:7 0.00999004 |
| 5 *21:5 0.0313353 |
| 6 *419:io_in[28] *40:13 0.000169942 |
| 7 *419:io_in[28] *55:16 0.000984306 |
| 8 *419:io_in[28] *57:11 0.00380797 |
| 9 *419:io_in[28] *61:11 1.47681e-05 |
| 10 *419:io_in[28] *70:5 0.000403897 |
| 11 *21:5 *24:19 0.015471 |
| 12 *21:5 *69:5 0.030198 |
| 13 *21:9 *24:19 0.0113933 |
| 14 *21:9 *35:19 0.00839718 |
| 15 *21:9 *55:16 0.000231272 |
| 16 *21:9 *69:5 0 |
| 17 *21:9 *70:5 0.00768583 |
| 18 *21:9 *79:13 0.00169236 |
| 19 *21:9 *81:13 0.00363516 |
| 20 *21:9 *98:9 0.00120003 |
| 21 *17:16 *419:io_in[28] 0.000266183 |
| *RES |
| 1 io_in[28] *21:5 353.115 |
| 2 *21:5 *21:7 0.63 |
| 3 *21:7 *21:9 147.78 |
| 4 *21:9 *419:io_in[28] 36.99 |
| *END |
| |
| *D_NET *22 0.206543 |
| *CONN |
| *P io_in[29] I |
| *I *419:io_in[29] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[29] 0.000177869 |
| 2 *419:io_in[29] 0.000272478 |
| 3 *22:19 0.00222394 |
| 4 *22:18 0.00195146 |
| 5 *22:16 0.00790188 |
| 6 *22:15 0.00790188 |
| 7 *22:13 0.0462751 |
| 8 *22:11 0.046453 |
| 9 *22:13 *67:7 0 |
| 10 *22:19 *42:8 0.0420664 |
| 11 *22:19 *44:8 0.0261125 |
| 12 *22:19 *60:14 0.00181316 |
| 13 *22:19 *95:8 0.0155234 |
| 14 *22:19 *114:11 0.00367313 |
| 15 *10:14 *22:19 0.00419659 |
| *RES |
| 1 io_in[29] *22:11 1.935 |
| 2 *22:11 *22:13 359.91 |
| 3 *22:13 *22:15 4.5 |
| 4 *22:15 *22:16 60.21 |
| 5 *22:16 *22:18 4.5 |
| 6 *22:18 *22:19 140.49 |
| 7 *22:19 *419:io_in[29] 6.165 |
| *END |
| |
| *D_NET *23 0.23169 |
| *CONN |
| *P io_in[2] I |
| *I *419:io_in[2] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[2] 0.000167227 |
| 2 *419:io_in[2] 0.000304304 |
| 3 *23:19 0.0330084 |
| 4 *23:18 0.0327041 |
| 5 *23:16 0.05761 |
| 6 *23:15 0.05761 |
| 7 *23:13 0.0250593 |
| 8 *23:11 0.0252265 |
| *RES |
| 1 io_in[2] *23:11 2.115 |
| 2 *23:11 *23:13 197.37 |
| 3 *23:13 *23:15 4.5 |
| 4 *23:15 *23:16 442.89 |
| 5 *23:16 *23:18 4.5 |
| 6 *23:18 *23:19 253.71 |
| 7 *23:19 *419:io_in[2] 11.52 |
| *END |
| |
| *D_NET *24 0.219436 |
| *CONN |
| *P io_in[30] I |
| *I *419:io_in[30] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[30] 0.00312894 |
| 2 *419:io_in[30] 0.000212844 |
| 3 *24:19 0.0404357 |
| 4 *24:18 0.0402229 |
| 5 *24:16 0.0179418 |
| 6 *24:15 0.0210707 |
| 7 *24:15 *314:16 0 |
| 8 *24:16 *28:16 0.000245553 |
| 9 *24:19 *81:13 0.00362864 |
| 10 *24:19 *98:9 0.0656846 |
| 11 *21:5 *24:19 0.015471 |
| 12 *21:9 *24:19 0.0113933 |
| *RES |
| 1 io_in[30] *24:15 28.665 |
| 2 *24:15 *24:16 137.79 |
| 3 *24:16 *24:18 4.5 |
| 4 *24:18 *24:19 411.75 |
| 5 *24:19 *419:io_in[30] 14.76 |
| *END |
| |
| *D_NET *25 0.137386 |
| *CONN |
| *P io_in[31] I |
| *I *419:io_in[31] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[31] 0.00177706 |
| 2 *419:io_in[31] 2.87269e-05 |
| 3 *25:12 0.0101903 |
| 4 *25:11 0.0101615 |
| 5 *25:9 0.0567257 |
| 6 *25:7 0.0585027 |
| 7 *25:9 *73:10 0 |
| *RES |
| 1 io_in[31] *25:7 13.185 |
| 2 *25:7 *25:9 442.98 |
| 3 *25:9 *25:11 4.5 |
| 4 *25:11 *25:12 76.59 |
| 5 *25:12 *419:io_in[31] 0.225 |
| *END |
| |
| *D_NET *26 0.247075 |
| *CONN |
| *P io_in[32] I |
| *I *419:io_in[32] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[32] 0.000323383 |
| 2 *419:io_in[32] 0.00137109 |
| 3 *26:16 0.0153798 |
| 4 *26:15 0.0140087 |
| 5 *26:13 0.0661719 |
| 6 *26:11 0.0664953 |
| 7 *26:16 *66:11 0.0833249 |
| *RES |
| 1 io_in[32] *26:11 3.015 |
| 2 *26:11 *26:13 515.43 |
| 3 *26:13 *26:15 4.5 |
| 4 *26:15 *26:16 212.31 |
| 5 *26:16 *419:io_in[32] 23.94 |
| *END |
| |
| *D_NET *27 0.172662 |
| *CONN |
| *P io_in[33] I |
| *I *419:io_in[33] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[33] 0.00385806 |
| 2 *419:io_in[33] 0.0449257 |
| 3 *27:18 0.0449257 |
| 4 *27:16 0.0375471 |
| 5 *27:15 0.0414052 |
| *RES |
| 1 io_in[33] *27:15 34.785 |
| 2 *27:15 *27:16 288.45 |
| 3 *27:16 *27:18 4.5 |
| 4 *27:18 *419:io_in[33] 349.785 |
| *END |
| |
| *D_NET *28 0.284626 |
| *CONN |
| *P io_in[34] I |
| *I *419:io_in[34] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[34] 0.00312523 |
| 2 *419:io_in[34] 0.00113798 |
| 3 *28:19 0.0265461 |
| 4 *28:18 0.0254082 |
| 5 *28:16 0.0356061 |
| 6 *28:15 0.0387313 |
| 7 *28:19 *314:16 0.153825 |
| 8 *24:16 *28:16 0.000245553 |
| *RES |
| 1 io_in[34] *28:15 28.845 |
| 2 *28:15 *28:16 274.23 |
| 3 *28:16 *28:18 4.5 |
| 4 *28:18 *28:19 385.11 |
| 5 *28:19 *419:io_in[34] 12.105 |
| *END |
| |
| *D_NET *29 0.20037 |
| *CONN |
| *P io_in[35] I |
| *I *419:io_in[35] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[35] 0.000113196 |
| 2 *419:io_in[35] 0.000304505 |
| 3 *29:22 0.042473 |
| 4 *29:21 0.0421685 |
| 5 *29:19 0.0123923 |
| 6 *29:18 0.015682 |
| 7 *29:13 0.0450899 |
| 8 *29:11 0.0419134 |
| 9 *29:18 *105:15 0.000233283 |
| *RES |
| 1 io_in[35] *29:11 1.395 |
| 2 *29:11 *29:13 327.51 |
| 3 *29:13 *29:18 34.65 |
| 4 *29:18 *29:19 96.03 |
| 5 *29:19 *29:21 4.5 |
| 6 *29:21 *29:22 323.73 |
| 7 *29:22 *419:io_in[35] 2.385 |
| *END |
| |
| *D_NET *30 0.245402 |
| *CONN |
| *P io_in[36] I |
| *I *419:io_in[36] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[36] 0.00177706 |
| 2 *419:io_in[36] 0.0012664 |
| 3 *30:12 0.0571561 |
| 4 *30:11 0.0558897 |
| 5 *30:9 0.063768 |
| 6 *30:7 0.0655451 |
| 7 *1:12 *30:12 0 |
| *RES |
| 1 io_in[36] *30:7 13.185 |
| 2 *30:7 *30:9 499.68 |
| 3 *30:9 *30:11 4.5 |
| 4 *30:11 *30:12 429.39 |
| 5 *30:12 *419:io_in[36] 21.06 |
| *END |
| |
| *D_NET *31 0.249294 |
| *CONN |
| *P io_in[37] I |
| *I *419:io_in[37] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[37] 0.000323383 |
| 2 *419:io_in[37] 0.00584209 |
| 3 *31:16 0.0817619 |
| 4 *31:15 0.0759198 |
| 5 *31:13 0.0425619 |
| 6 *31:11 0.0428853 |
| *RES |
| 1 io_in[37] *31:11 3.015 |
| 2 *31:11 *31:13 332.91 |
| 3 *31:13 *31:15 4.5 |
| 4 *31:15 *31:16 583.83 |
| 5 *31:16 *419:io_in[37] 49.185 |
| *END |
| |
| *D_NET *32 0.313774 |
| *CONN |
| *P io_in[3] I |
| *I *419:io_in[3] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[3] 0.0520036 |
| 2 *419:io_in[3] 0.0003399 |
| 3 *32:11 0.00327423 |
| 4 *32:10 0.00293433 |
| 5 *32:8 0.0613904 |
| 6 *32:7 0.0613904 |
| 7 *32:5 0.0520036 |
| 8 *32:11 *35:19 0.000719881 |
| 9 *32:11 *37:11 0.0268173 |
| 10 *32:11 *38:19 0.0332252 |
| 11 *32:11 *98:9 0.0150195 |
| 12 *7:8 *32:11 0.00465589 |
| *RES |
| 1 io_in[3] *32:5 407.925 |
| 2 *32:5 *32:7 4.5 |
| 3 *32:7 *32:8 470.25 |
| 4 *32:8 *32:10 4.5 |
| 5 *32:10 *32:11 132.75 |
| 6 *32:11 *419:io_in[3] 15.12 |
| *END |
| |
| *D_NET *33 0.200384 |
| *CONN |
| *P io_in[4] I |
| *I *419:io_in[4] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[4] 0.0002319 |
| 2 *419:io_in[4] 0.000304304 |
| 3 *33:19 0.0419925 |
| 4 *33:18 0.0416882 |
| 5 *33:16 0.041843 |
| 6 *33:15 0.041843 |
| 7 *33:13 0.0161246 |
| 8 *33:11 0.0163565 |
| *RES |
| 1 io_in[4] *33:11 2.655 |
| 2 *33:11 *33:13 127.17 |
| 3 *33:13 *33:15 4.5 |
| 4 *33:15 *33:16 321.39 |
| 5 *33:16 *33:18 4.5 |
| 6 *33:18 *33:19 323.91 |
| 7 *33:19 *419:io_in[4] 11.52 |
| *END |
| |
| *D_NET *34 0.189837 |
| *CONN |
| *P io_in[5] I |
| *I *419:io_in[5] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[5] 0.00466579 |
| 2 *419:io_in[5] 0.000174631 |
| 3 *34:15 0.042122 |
| 4 *34:14 0.0419474 |
| 5 *34:12 0.0369241 |
| 6 *34:11 0.0369241 |
| 7 *34:9 0.0112064 |
| 8 *34:7 0.0158722 |
| *RES |
| 1 io_in[5] *34:7 37.305 |
| 2 *34:7 *34:9 87.84 |
| 3 *34:9 *34:11 4.5 |
| 4 *34:11 *34:12 283.59 |
| 5 *34:12 *34:14 4.5 |
| 6 *34:14 *34:15 326.61 |
| 7 *34:15 *419:io_in[5] 10.44 |
| *END |
| |
| *D_NET *35 0.235497 |
| *CONN |
| *P io_in[6] I |
| *I *419:io_in[6] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[6] 0.000370905 |
| 2 *419:io_in[6] 0.000212844 |
| 3 *35:19 0.00418474 |
| 4 *35:18 0.0039719 |
| 5 *35:16 0.0367822 |
| 6 *35:15 0.0367822 |
| 7 *35:13 0.0527243 |
| 8 *35:11 0.0530952 |
| 9 *35:16 *47:13 0 |
| 10 *35:19 *38:19 0.0311681 |
| 11 *35:19 *40:13 0.000219217 |
| 12 *35:19 *55:16 0.00362994 |
| 13 *35:19 *70:5 0 |
| 14 *35:19 *98:9 0.00323799 |
| 15 *35:19 *112:21 0 |
| 16 *21:9 *35:19 0.00839718 |
| 17 *32:11 *35:19 0.000719881 |
| *RES |
| 1 io_in[6] *35:11 3.195 |
| 2 *35:11 *35:13 413.37 |
| 3 *35:13 *35:15 4.5 |
| 4 *35:15 *35:16 280.89 |
| 5 *35:16 *35:18 4.5 |
| 6 *35:18 *35:19 96.03 |
| 7 *35:19 *419:io_in[6] 14.76 |
| *END |
| |
| *D_NET *36 0.152832 |
| *CONN |
| *P io_in[7] I |
| *I *419:io_in[7] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[7] 0.000167227 |
| 2 *419:io_in[7] 0.000471367 |
| 3 *36:19 0.0428063 |
| 4 *36:18 0.0423349 |
| 5 *36:16 0.0179623 |
| 6 *36:15 0.0179623 |
| 7 *36:13 0.0154799 |
| 8 *36:11 0.0156472 |
| *RES |
| 1 io_in[7] *36:11 2.115 |
| 2 *36:11 *36:13 121.77 |
| 3 *36:13 *36:15 4.5 |
| 4 *36:15 *36:16 137.79 |
| 5 *36:16 *36:18 4.5 |
| 6 *36:18 *36:19 329.31 |
| 7 *36:19 *419:io_in[7] 12.06 |
| *END |
| |
| *D_NET *37 0.189911 |
| *CONN |
| *P io_in[8] I |
| *I *419:io_in[8] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[8] 0.0559527 |
| 2 *419:io_in[8] 0.000347463 |
| 3 *37:11 0.00248941 |
| 4 *37:10 0.00214194 |
| 5 *37:8 0.0201446 |
| 6 *37:7 0.0201446 |
| 7 *37:5 0.0559527 |
| 8 *7:8 *37:11 0.00592003 |
| 9 *32:11 *37:11 0.0268173 |
| *RES |
| 1 io_in[8] *37:5 437.625 |
| 2 *37:5 *37:7 4.5 |
| 3 *37:7 *37:8 151.83 |
| 4 *37:8 *37:10 4.5 |
| 5 *37:10 *37:11 67.41 |
| 6 *37:11 *419:io_in[8] 15.21 |
| *END |
| |
| *D_NET *38 0.195661 |
| *CONN |
| *P io_in[9] I |
| *I *419:io_in[9] I *D wrapped_vga_clock |
| *CAP |
| 1 io_in[9] 0.000251703 |
| 2 *419:io_in[9] 0.000270277 |
| 3 *38:19 0.00165925 |
| 4 *38:18 0.00138897 |
| 5 *38:16 0.0117877 |
| 6 *38:15 0.0117877 |
| 7 *38:13 0.0519086 |
| 8 *38:11 0.0521603 |
| 9 *38:19 *112:21 0 |
| 10 *7:8 *38:19 5.34641e-05 |
| 11 *32:11 *38:19 0.0332252 |
| 12 *35:19 *38:19 0.0311681 |
| *RES |
| 1 io_in[9] *38:11 2.655 |
| 2 *38:11 *38:13 405.27 |
| 3 *38:13 *38:15 4.5 |
| 4 *38:15 *38:16 89.37 |
| 5 *38:16 *38:18 4.5 |
| 6 *38:18 *38:19 91.17 |
| 7 *38:19 *419:io_in[9] 14.85 |
| *END |
| |
| *D_NET *39 0.295576 |
| *CONN |
| *P io_oeb[0] O |
| *I *419:io_oeb[0] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[0] 0.0554063 |
| 2 *419:io_oeb[0] 0.000809232 |
| 3 *39:16 0.0554063 |
| 4 *39:14 0.0811587 |
| 5 *39:13 0.0838289 |
| 6 *39:10 0.00347936 |
| 7 *39:13 *97:11 0.00169771 |
| 8 *39:13 *111:11 0.00295238 |
| 9 *39:13 *112:15 0.0108371 |
| *RES |
| 1 *419:io_oeb[0] *39:10 18.18 |
| 2 *39:10 *39:13 47.61 |
| 3 *39:13 *39:14 621.81 |
| 4 *39:14 *39:16 4.5 |
| 5 *39:16 io_oeb[0] 434.925 |
| *END |
| |
| *D_NET *40 0.124517 |
| *CONN |
| *P io_oeb[10] O |
| *I *419:io_oeb[10] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[10] 0.0563618 |
| 2 *419:io_oeb[10] 0.00347242 |
| 3 *40:13 0.0598342 |
| 4 *40:13 *55:16 0.000183693 |
| 5 *40:13 *70:5 0.00427583 |
| 6 *419:io_in[28] *40:13 0.000169942 |
| 7 *3:19 io_oeb[10] 0 |
| 8 *35:19 *40:13 0.000219217 |
| *RES |
| 1 *419:io_oeb[10] *40:13 45.405 |
| 2 *40:13 io_oeb[10] 440.325 |
| *END |
| |
| *D_NET *41 0.222072 |
| *CONN |
| *P io_oeb[11] O |
| *I *419:io_oeb[11] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[11] 0.000210342 |
| 2 *419:io_oeb[11] 0.000216197 |
| 3 *41:16 0.0164378 |
| 4 *41:15 0.0162275 |
| 5 *41:13 0.0137556 |
| 6 *41:12 0.0137556 |
| 7 *41:10 0.0240138 |
| 8 *41:9 0.02423 |
| 9 *2:9 *41:10 0.113225 |
| 10 *8:13 *41:13 0 |
| *RES |
| 1 *419:io_oeb[11] *41:9 10.8 |
| 2 *41:9 *41:10 323.91 |
| 3 *41:10 *41:12 4.5 |
| 4 *41:12 *41:13 105.21 |
| 5 *41:13 *41:15 4.5 |
| 6 *41:15 *41:16 127.17 |
| 7 *41:16 io_oeb[11] 2.475 |
| *END |
| |
| *D_NET *42 0.294272 |
| *CONN |
| *P io_oeb[12] O |
| *I *419:io_oeb[12] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[12] 0.00466139 |
| 2 *419:io_oeb[12] 0.000233519 |
| 3 *42:14 0.051089 |
| 4 *42:13 0.0464276 |
| 5 *42:11 0.036165 |
| 6 *42:10 0.036165 |
| 7 *42:8 0.00123195 |
| 8 *42:7 0.00146547 |
| 9 *42:8 *44:8 0.010263 |
| 10 *42:8 *114:11 0.0645036 |
| 11 *22:19 *42:8 0.0420664 |
| *RES |
| 1 *419:io_oeb[12] *42:7 5.985 |
| 2 *42:7 *42:8 162.45 |
| 3 *42:8 *42:10 4.5 |
| 4 *42:10 *42:11 276.03 |
| 5 *42:11 *42:13 4.5 |
| 6 *42:13 *42:14 363.24 |
| 7 *42:14 io_oeb[12] 37.125 |
| *END |
| |
| *D_NET *43 0.227094 |
| *CONN |
| *P io_oeb[13] O |
| *I *419:io_oeb[13] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[13] 0.000275016 |
| 2 *419:io_oeb[13] 0.00196472 |
| 3 *43:17 0.0562159 |
| 4 *43:16 0.0559409 |
| 5 *43:14 0.0254357 |
| 6 *43:13 0.0254357 |
| 7 *43:11 0.00903607 |
| 8 *43:10 0.0110008 |
| 9 *43:11 *51:11 0.0035099 |
| 10 *13:14 *43:11 0.0382789 |
| *RES |
| 1 *419:io_oeb[13] *43:10 26.82 |
| 2 *43:10 *43:11 120.51 |
| 3 *43:11 *43:13 4.5 |
| 4 *43:13 *43:14 195.93 |
| 5 *43:14 *43:16 4.5 |
| 6 *43:16 *43:17 437.67 |
| 7 *43:17 io_oeb[13] 3.015 |
| *END |
| |
| *D_NET *44 0.291462 |
| *CONN |
| *P io_oeb[14] O |
| *I *419:io_oeb[14] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[14] 0.000145669 |
| 2 *419:io_oeb[14] 0.000311436 |
| 3 *44:14 0.0497397 |
| 4 *44:13 0.0495941 |
| 5 *44:11 0.0527518 |
| 6 *44:10 0.0527518 |
| 7 *44:8 0.00301695 |
| 8 *44:7 0.00332838 |
| 9 *44:8 *113:14 0 |
| 10 *44:8 *114:11 0.00130753 |
| 11 *10:14 *44:8 0.0421392 |
| 12 *22:19 *44:8 0.0261125 |
| 13 *42:8 *44:8 0.010263 |
| *RES |
| 1 *419:io_oeb[14] *44:7 6.345 |
| 2 *44:7 *44:8 133.29 |
| 3 *44:8 *44:10 4.5 |
| 4 *44:10 *44:11 403.29 |
| 5 *44:11 *44:13 4.5 |
| 6 *44:13 *44:14 389.07 |
| 7 *44:14 io_oeb[14] 1.935 |
| *END |
| |
| *D_NET *45 0.248887 |
| *CONN |
| *P io_oeb[15] O |
| *I *419:io_oeb[15] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[15] 0.00029378 |
| 2 *419:io_oeb[15] 0.000736014 |
| 3 *45:17 0.0527393 |
| 4 *45:16 0.0524455 |
| 5 *45:14 0.0435149 |
| 6 *45:13 0.0456935 |
| 7 *45:8 0.00349871 |
| 8 *45:7 0.00205613 |
| 9 *45:8 *59:8 0.00416231 |
| 10 *45:8 *75:11 0.00882207 |
| 11 *45:8 *78:8 0.0210228 |
| 12 *45:8 *86:8 0.00165215 |
| 13 *45:8 *90:8 0.00344471 |
| 14 *45:8 *113:13 0.00880485 |
| *RES |
| 1 *419:io_oeb[15] *45:7 9.045 |
| 2 *45:7 *45:8 75.51 |
| 3 *45:8 *45:13 24.75 |
| 4 *45:13 *45:14 339.03 |
| 5 *45:14 *45:16 4.5 |
| 6 *45:16 *45:17 402.57 |
| 7 *45:17 io_oeb[15] 3.015 |
| *END |
| |
| *D_NET *46 0.158763 |
| *CONN |
| *P io_oeb[16] O |
| *I *419:io_oeb[16] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[16] 0.00516895 |
| 2 *419:io_oeb[16] 0.000160537 |
| 3 *46:11 0.0436673 |
| 4 *46:10 0.0384983 |
| 5 *46:8 0.0355539 |
| 6 *46:7 0.0357144 |
| *RES |
| 1 *419:io_oeb[16] *46:7 9.81 |
| 2 *46:7 *46:8 224.01 |
| 3 *46:8 *46:10 4.5 |
| 4 *46:10 *46:11 295.65 |
| 5 *46:11 io_oeb[16] 49.455 |
| *END |
| |
| *D_NET *47 0.180647 |
| *CONN |
| *P io_oeb[17] O |
| *I *419:io_oeb[17] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[17] 0.0539412 |
| 2 *419:io_oeb[17] 0.000690065 |
| 3 *47:16 0.0539412 |
| 4 *47:14 0.0143237 |
| 5 *47:13 0.0150075 |
| 6 *47:8 0.00102399 |
| 7 *47:7 0.00103023 |
| 8 *47:8 *78:8 0.0210863 |
| 9 *47:8 *84:8 0.00128375 |
| 10 *47:8 *86:8 0.0183187 |
| 11 *47:14 *114:11 0 |
| 12 *35:16 *47:13 0 |
| *RES |
| 1 *419:io_oeb[17] *47:7 8.685 |
| 2 *47:7 *47:8 53.19 |
| 3 *47:8 *47:13 13.59 |
| 4 *47:13 *47:14 110.79 |
| 5 *47:14 *47:16 4.5 |
| 6 *47:16 io_oeb[17] 413.325 |
| *END |
| |
| *D_NET *48 0.100297 |
| *CONN |
| *P io_oeb[18] O |
| *I *419:io_oeb[18] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[18] 0.000224836 |
| 2 *419:io_oeb[18] 0.0029127 |
| 3 *48:17 0.0360549 |
| 4 *48:16 0.0379541 |
| 5 *48:11 0.00953903 |
| 6 *48:10 0.0103276 |
| 7 *48:11 *76:13 1.0415e-05 |
| 8 *9:14 *48:16 0.0032737 |
| *RES |
| 1 *419:io_oeb[18] *48:10 35.82 |
| 2 *48:10 *48:11 55.35 |
| 3 *48:11 *48:16 29.43 |
| 4 *48:16 *48:17 275.67 |
| 5 *48:17 io_oeb[18] 2.475 |
| *END |
| |
| *D_NET *49 0.0786683 |
| *CONN |
| *P io_oeb[19] O |
| *I *419:io_oeb[19] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[19] 0.00223028 |
| 2 *419:io_oeb[19] 9.85257e-05 |
| 3 *49:8 0.0384566 |
| 4 *49:7 0.0363248 |
| 5 io_oeb[19] *87:11 0.00155819 |
| *RES |
| 1 *419:io_oeb[19] *49:7 9.63 |
| 2 *49:7 *49:8 276.75 |
| 3 *49:8 io_oeb[19] 30.555 |
| *END |
| |
| *D_NET *50 0.319731 |
| *CONN |
| *P io_oeb[1] O |
| *I *419:io_oeb[1] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[1] 0.000210342 |
| 2 *419:io_oeb[1] 0.00077237 |
| 3 *50:11 0.074784 |
| 4 *50:10 0.0745736 |
| 5 *50:8 0.0534849 |
| 6 *50:7 0.0542573 |
| 7 *50:8 io_out[20] 0.0237644 |
| 8 *50:8 *74:8 0.0378845 |
| *RES |
| 1 *419:io_oeb[1] *50:7 10.125 |
| 2 *50:7 *50:8 488.79 |
| 3 *50:8 *50:10 4.5 |
| 4 *50:10 *50:11 584.91 |
| 5 *50:11 io_oeb[1] 2.475 |
| *END |
| |
| *D_NET *51 0.0969186 |
| *CONN |
| *P io_oeb[20] O |
| *I *419:io_oeb[20] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[20] 0.00029378 |
| 2 *419:io_oeb[20] 0.00203565 |
| 3 *51:14 0.0357451 |
| 4 *51:13 0.0354513 |
| 5 *51:11 0.0089236 |
| 6 *51:10 0.0109592 |
| 7 *51:10 *56:14 0 |
| 8 *43:11 *51:11 0.0035099 |
| *RES |
| 1 *419:io_oeb[20] *51:10 27 |
| 2 *51:10 *51:11 73.17 |
| 3 *51:11 *51:13 4.5 |
| 4 *51:13 *51:14 272.79 |
| 5 *51:14 io_oeb[20] 3.015 |
| *END |
| |
| *D_NET *52 0.158176 |
| *CONN |
| *P io_oeb[21] O |
| *I *419:io_oeb[21] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[21] 0.000155891 |
| 2 *419:io_oeb[21] 0.00127222 |
| 3 *52:14 0.0362787 |
| 4 *52:13 0.0361228 |
| 5 *52:11 0.0152272 |
| 6 *52:10 0.0164994 |
| 7 *52:11 *91:17 0.0253622 |
| 8 *4:11 *52:11 0.000893611 |
| 9 *8:16 *52:11 0.0263641 |
| *RES |
| 1 *419:io_oeb[21] *52:10 21.78 |
| 2 *52:10 *52:11 214.11 |
| 3 *52:11 *52:13 4.5 |
| 4 *52:13 *52:14 278.01 |
| 5 *52:14 io_oeb[21] 1.935 |
| *END |
| |
| *D_NET *53 0.219796 |
| *CONN |
| *P io_oeb[22] O |
| *I *419:io_oeb[22] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[22] 0.0541897 |
| 2 *419:io_oeb[22] 0.000596172 |
| 3 *53:16 0.0541897 |
| 4 *53:14 0.0238489 |
| 5 *53:13 0.0239619 |
| 6 *53:8 0.0069733 |
| 7 *53:7 0.00745641 |
| 8 *53:8 *86:8 0.0140862 |
| 9 *53:8 *90:8 0.00686625 |
| 10 *53:13 *73:7 0.000595722 |
| 11 *53:14 *58:8 0 |
| 12 *53:14 *60:14 0 |
| 13 *53:14 *95:8 0.0270321 |
| 14 *10:14 *53:8 0 |
| *RES |
| 1 *419:io_oeb[22] *53:7 8.325 |
| 2 *53:7 *53:8 90.27 |
| 3 *53:8 *53:13 10.53 |
| 4 *53:13 *53:14 264.87 |
| 5 *53:14 *53:16 4.5 |
| 6 *53:16 io_oeb[22] 416.025 |
| *END |
| |
| *D_NET *54 0.251402 |
| *CONN |
| *P io_oeb[23] O |
| *I *419:io_oeb[23] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[23] 0.00107486 |
| 2 *419:io_oeb[23] 0.000813382 |
| 3 *54:14 0.0408124 |
| 4 *54:13 0.0397375 |
| 5 *54:11 0.0536344 |
| 6 *54:10 0.0536344 |
| 7 *54:8 0.000493125 |
| 8 *54:7 0.00130651 |
| 9 *54:8 *59:8 0.00931737 |
| 10 *54:8 *90:8 0.0202342 |
| 11 *54:11 *91:16 0 |
| 12 *54:14 *90:14 0.0300889 |
| 13 *14:10 *54:14 0.000254726 |
| *RES |
| 1 *419:io_oeb[23] *54:7 9.045 |
| 2 *54:7 *54:8 50.85 |
| 3 *54:8 *54:10 4.5 |
| 4 *54:10 *54:11 409.95 |
| 5 *54:11 *54:13 4.5 |
| 6 *54:13 *54:14 347.85 |
| 7 *54:14 io_oeb[23] 12.825 |
| *END |
| |
| *D_NET *55 0.250173 |
| *CONN |
| *P io_oeb[24] O |
| *I *419:io_oeb[24] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[24] 0.000242542 |
| 2 *419:io_oeb[24] 0.000672876 |
| 3 *55:20 0.0642962 |
| 4 *55:19 0.0640537 |
| 5 *55:17 0.0291567 |
| 6 *55:16 0.0295386 |
| 7 *55:11 0.00543743 |
| 8 *55:10 0.00572845 |
| 9 *55:17 *61:11 0.00109959 |
| 10 *419:io_in[28] *55:16 0.000984306 |
| 11 *13:17 *55:11 0.0369186 |
| 12 *17:28 *55:11 0.0079988 |
| 13 *21:9 *55:16 0.000231272 |
| 14 *35:19 *55:16 0.00362994 |
| 15 *40:13 *55:16 0.000183693 |
| *RES |
| 1 *419:io_oeb[24] *55:10 18.54 |
| 2 *55:10 *55:11 94.41 |
| 3 *55:11 *55:16 18.81 |
| 4 *55:16 *55:17 224.37 |
| 5 *55:17 *55:19 4.5 |
| 6 *55:19 *55:20 500.31 |
| 7 *55:20 io_oeb[24] 2.475 |
| *END |
| |
| *D_NET *56 0.150811 |
| *CONN |
| *P io_oeb[25] O |
| *I *419:io_oeb[25] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[25] 0.000177869 |
| 2 *419:io_oeb[25] 0.000785345 |
| 3 *56:17 0.0521641 |
| 4 *56:16 0.0519862 |
| 5 *56:14 0.0201053 |
| 6 *56:13 0.0208907 |
| 7 *56:13 *111:11 0.00235462 |
| 8 *56:13 *112:13 0.00234692 |
| 9 *51:10 *56:14 0 |
| *RES |
| 1 *419:io_oeb[25] *56:13 28.53 |
| 2 *56:13 *56:14 153.45 |
| 3 *56:14 *56:16 4.5 |
| 4 *56:16 *56:17 405.81 |
| 5 *56:17 io_oeb[25] 1.935 |
| *END |
| |
| *D_NET *57 0.168078 |
| *CONN |
| *P io_oeb[26] O |
| *I *419:io_oeb[26] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[26] 0.000113196 |
| 2 *419:io_oeb[26] 0.000276453 |
| 3 *57:14 0.0652115 |
| 4 *57:13 0.0650983 |
| 5 *57:11 0.0166062 |
| 6 *57:10 0.0168827 |
| 7 *57:11 *112:20 8.2093e-05 |
| 8 *419:io_in[28] *57:11 0.00380797 |
| 9 *17:16 *57:11 0 |
| *RES |
| 1 *419:io_oeb[26] *57:10 15.66 |
| 2 *57:10 *57:11 129.69 |
| 3 *57:11 *57:13 4.5 |
| 4 *57:13 *57:14 507.15 |
| 5 *57:14 io_oeb[26] 1.395 |
| *END |
| |
| *D_NET *58 0.235757 |
| *CONN |
| *P io_oeb[27] O |
| *I *419:io_oeb[27] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[27] 0.00323529 |
| 2 *419:io_oeb[27] 0.000580167 |
| 3 *58:11 0.0233723 |
| 4 *58:10 0.020137 |
| 5 *58:8 0.0246247 |
| 6 *58:7 0.0252048 |
| 7 *58:8 *90:8 0.000563374 |
| 8 *58:8 *96:8 0.13804 |
| 9 *53:14 *58:8 0 |
| *RES |
| 1 *419:io_oeb[27] *58:7 8.325 |
| 2 *58:7 *58:8 360.81 |
| 3 *58:8 *58:10 4.5 |
| 4 *58:10 *58:11 154.35 |
| 5 *58:11 io_oeb[27] 29.565 |
| *END |
| |
| *D_NET *59 0.186221 |
| *CONN |
| *P io_oeb[28] O |
| *I *419:io_oeb[28] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[28] 0.000350338 |
| 2 *419:io_oeb[28] 0.000829907 |
| 3 *59:14 0.0577475 |
| 4 *59:13 0.0573971 |
| 5 *59:11 0.0112178 |
| 6 *59:10 0.0112178 |
| 7 *59:8 0.00977236 |
| 8 *59:7 0.0106023 |
| 9 *59:8 *90:8 0.00478645 |
| 10 *59:8 *99:10 0 |
| 11 *59:8 *113:13 0.00882026 |
| 12 *45:8 *59:8 0.00416231 |
| 13 *54:8 *59:8 0.00931737 |
| *RES |
| 1 *419:io_oeb[28] *59:7 9.405 |
| 2 *59:7 *59:8 133.47 |
| 3 *59:8 *59:10 4.5 |
| 4 *59:10 *59:11 85.05 |
| 5 *59:11 *59:13 4.5 |
| 6 *59:13 *59:14 362.61 |
| 7 *59:14 io_oeb[28] 3.015 |
| *END |
| |
| *D_NET *60 0.189976 |
| *CONN |
| *P io_oeb[29] O |
| *I *419:io_oeb[29] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[29] 0.00288658 |
| 2 *419:io_oeb[29] 0.00218004 |
| 3 *60:14 0.0516956 |
| 4 *60:13 0.0509891 |
| 5 *60:13 *314:19 0.0104362 |
| 6 *60:14 *89:10 0 |
| 7 *60:14 *95:8 0.0167662 |
| 8 *60:14 *101:16 0.000322893 |
| 9 *60:14 *114:11 0.0528861 |
| 10 *22:19 *60:14 0.00181316 |
| 11 *53:14 *60:14 0 |
| *RES |
| 1 *419:io_oeb[29] *60:13 47.25 |
| 2 *60:13 *60:14 501.39 |
| 3 *60:14 io_oeb[29] 30.735 |
| *END |
| |
| *D_NET *61 0.255754 |
| *CONN |
| *P io_oeb[2] O |
| *I *419:io_oeb[2] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[2] 0.00464423 |
| 2 *419:io_oeb[2] 0.0024903 |
| 3 *61:17 0.0544228 |
| 4 *61:16 0.0497786 |
| 5 *61:14 0.0645348 |
| 6 *61:13 0.0645348 |
| 7 *61:11 0.0024903 |
| 8 *61:11 *110:11 0.0117437 |
| 9 *419:io_in[28] *61:11 1.47681e-05 |
| 10 *7:8 *61:11 0 |
| 11 *11:16 *61:11 0 |
| 12 *55:17 *61:11 0.00109959 |
| *RES |
| 1 *419:io_oeb[2] *61:11 47.07 |
| 2 *61:11 *61:13 4.5 |
| 3 *61:13 *61:14 494.19 |
| 4 *61:14 *61:16 4.5 |
| 5 *61:16 *61:17 390.24 |
| 6 *61:17 io_oeb[2] 37.125 |
| *END |
| |
| *D_NET *62 0.139743 |
| *CONN |
| *P io_oeb[30] O |
| *I *419:io_oeb[30] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[30] 0.00117627 |
| 2 *419:io_oeb[30] 0.0424006 |
| 3 *62:8 0.0218572 |
| 4 *62:7 0.0206809 |
| 5 *62:5 0.0424006 |
| 6 *62:5 *97:17 0.0112277 |
| *RES |
| 1 *419:io_oeb[30] *62:5 368.685 |
| 2 *62:5 *62:7 4.5 |
| 3 *62:7 *62:8 158.85 |
| 4 *62:8 io_oeb[30] 13.365 |
| *END |
| |
| *D_NET *63 0.185306 |
| *CONN |
| *P io_oeb[31] O |
| *I *419:io_oeb[31] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[31] 0.000149218 |
| 2 *419:io_oeb[31] 2.87269e-05 |
| 3 *63:10 0.0765243 |
| 4 *63:9 0.0763751 |
| 5 *63:7 0.0160999 |
| 6 *63:5 0.0161286 |
| *RES |
| 1 *419:io_oeb[31] *63:5 0.225 |
| 2 *63:5 *63:7 122.49 |
| 3 *63:7 *63:9 4.5 |
| 4 *63:9 *63:10 482.85 |
| 5 *63:10 io_oeb[31] 1.395 |
| *END |
| |
| *D_NET *64 0.160311 |
| *CONN |
| *P io_oeb[32] O |
| *I *419:io_oeb[32] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[32] 0.00311448 |
| 2 *419:io_oeb[32] 0.000166616 |
| 3 *64:10 0.0570735 |
| 4 *64:9 0.053959 |
| 5 *64:7 0.0229153 |
| 6 *64:5 0.0230819 |
| *RES |
| 1 *419:io_oeb[32] *64:5 1.305 |
| 2 *64:5 *64:7 175.23 |
| 3 *64:7 *64:9 4.5 |
| 4 *64:9 *64:10 421.29 |
| 5 *64:10 io_oeb[32] 30.915 |
| *END |
| |
| *D_NET *65 0.191527 |
| *CONN |
| *P io_oeb[33] O |
| *I *419:io_oeb[33] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[33] 0.000323383 |
| 2 *419:io_oeb[33] 0.00659049 |
| 3 *65:11 0.042154 |
| 4 *65:10 0.0418306 |
| 5 *65:8 0.0470192 |
| 6 *65:7 0.0470192 |
| 7 *65:5 0.00659049 |
| *RES |
| 1 *419:io_oeb[33] *65:5 50.085 |
| 2 *65:5 *65:7 4.5 |
| 3 *65:7 *65:8 361.35 |
| 4 *65:8 *65:10 4.5 |
| 5 *65:10 *65:11 327.51 |
| 6 *65:11 io_oeb[33] 3.015 |
| *END |
| |
| *D_NET *66 0.301633 |
| *CONN |
| *P io_oeb[34] O |
| *I *419:io_oeb[34] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[34] 0.000242542 |
| 2 *419:io_oeb[34] 0.00133235 |
| 3 *66:14 0.066187 |
| 4 *66:13 0.0659444 |
| 5 *66:11 0.0416346 |
| 6 *66:10 0.042967 |
| 7 *1:12 *66:11 0 |
| 8 *26:16 *66:11 0.0833249 |
| *RES |
| 1 *419:io_oeb[34] *66:10 23.76 |
| 2 *66:10 *66:11 424.53 |
| 3 *66:11 *66:13 4.5 |
| 4 *66:13 *66:14 515.25 |
| 5 *66:14 io_oeb[34] 2.475 |
| *END |
| |
| *D_NET *67 0.214747 |
| *CONN |
| *P io_oeb[35] O |
| *I *419:io_oeb[35] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[35] 0.000177869 |
| 2 *419:io_oeb[35] 0.00550152 |
| 3 *67:11 0.043076 |
| 4 *67:10 0.0428982 |
| 5 *67:8 0.0587959 |
| 6 *67:7 0.0642974 |
| 7 *22:13 *67:7 0 |
| *RES |
| 1 *419:io_oeb[35] *67:7 46.485 |
| 2 *67:7 *67:8 452.07 |
| 3 *67:8 *67:10 4.5 |
| 4 *67:10 *67:11 335.61 |
| 5 *67:11 io_oeb[35] 1.935 |
| *END |
| |
| *D_NET *68 0.2561 |
| *CONN |
| *P io_oeb[36] O |
| *I *419:io_oeb[36] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[36] 0.000113196 |
| 2 *419:io_oeb[36] 0.000728777 |
| 3 *68:14 0.0652691 |
| 4 *68:13 0.0651559 |
| 5 *68:11 0.0607766 |
| 6 *68:10 0.0615054 |
| 7 *68:11 *101:16 0.000826953 |
| 8 *419:io_in[20] *68:11 0.00172419 |
| *RES |
| 1 *419:io_oeb[36] *68:10 18.72 |
| 2 *68:10 *68:11 470.97 |
| 3 *68:11 *68:13 4.5 |
| 4 *68:13 *68:14 510.21 |
| 5 *68:14 io_oeb[36] 1.395 |
| *END |
| |
| *D_NET *69 0.273369 |
| *CONN |
| *P io_oeb[37] O |
| *I *419:io_oeb[37] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[37] 0.00192467 |
| 2 *419:io_oeb[37] 0.034201 |
| 3 *69:8 0.0873379 |
| 4 *69:7 0.0854132 |
| 5 *69:5 0.034201 |
| 6 *69:5 *79:13 9.29335e-05 |
| 7 *69:8 *313:13 0 |
| 8 *21:5 *69:5 0.030198 |
| 9 *21:9 *69:5 0 |
| *RES |
| 1 *419:io_oeb[37] *69:5 363.285 |
| 2 *69:5 *69:7 4.5 |
| 3 *69:7 *69:8 656.73 |
| 4 *69:8 io_oeb[37] 18.765 |
| *END |
| |
| *D_NET *70 0.267728 |
| *CONN |
| *P io_oeb[3] O |
| *I *419:io_oeb[3] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[3] 0.000275016 |
| 2 *419:io_oeb[3] 0 |
| 3 *70:11 0.053918 |
| 4 *70:10 0.053643 |
| 5 *70:8 0.0558901 |
| 6 *70:7 0.0558901 |
| 7 *70:5 0.0120372 |
| 8 *70:4 0.0120372 |
| 9 *70:5 *112:21 0.0116721 |
| 10 *419:io_in[28] *70:5 0.000403897 |
| 11 *21:9 *70:5 0.00768583 |
| 12 *35:19 *70:5 0 |
| 13 *40:13 *70:5 0.00427583 |
| *RES |
| 1 *419:io_oeb[3] *70:4 4.5 |
| 2 *70:4 *70:5 140.85 |
| 3 *70:5 *70:7 4.5 |
| 4 *70:7 *70:8 428.13 |
| 5 *70:8 *70:10 4.5 |
| 6 *70:10 *70:11 421.47 |
| 7 *70:11 io_oeb[3] 3.015 |
| *END |
| |
| *D_NET *71 0.236021 |
| *CONN |
| *P io_oeb[4] O |
| *I *419:io_oeb[4] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[4] 0.000145669 |
| 2 *419:io_oeb[4] 0.00114724 |
| 3 *71:11 0.0752658 |
| 4 *71:10 0.0751201 |
| 5 *71:8 0.0415974 |
| 6 *71:7 0.0427447 |
| *RES |
| 1 *419:io_oeb[4] *71:7 12.825 |
| 2 *71:7 *71:8 318.69 |
| 3 *71:8 *71:10 4.5 |
| 4 *71:10 *71:11 587.61 |
| 5 *71:11 io_oeb[4] 1.935 |
| *END |
| |
| *D_NET *72 0.169691 |
| *CONN |
| *P io_oeb[5] O |
| *I *419:io_oeb[5] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[5] 0.00307959 |
| 2 *419:io_oeb[5] 9.76714e-05 |
| 3 *72:10 0.0642355 |
| 4 *72:9 0.0611559 |
| 5 *72:7 0.0205124 |
| 6 *72:5 0.02061 |
| *RES |
| 1 *419:io_oeb[5] *72:5 0.765 |
| 2 *72:5 *72:7 156.33 |
| 3 *72:7 *72:9 4.5 |
| 4 *72:9 *72:10 477.99 |
| 5 *72:10 io_oeb[5] 33.255 |
| *END |
| |
| *D_NET *73 0.174696 |
| *CONN |
| *P io_oeb[6] O |
| *I *419:io_oeb[6] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[6] 0.00517816 |
| 2 *419:io_oeb[6] 0.00023556 |
| 3 *73:10 0.076962 |
| 4 *73:9 0.0717838 |
| 5 *73:7 0.00985248 |
| 6 *73:5 0.010088 |
| 7 *25:9 *73:10 0 |
| 8 *53:13 *73:7 0.000595722 |
| *RES |
| 1 *419:io_oeb[6] *73:5 1.845 |
| 2 *73:5 *73:7 75.33 |
| 3 *73:7 *73:9 4.5 |
| 4 *73:9 *73:10 560.25 |
| 5 *73:10 io_oeb[6] 49.275 |
| *END |
| |
| *D_NET *74 0.202682 |
| *CONN |
| *P io_oeb[7] O |
| *I *419:io_oeb[7] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[7] 0.00466139 |
| 2 *419:io_oeb[7] 0.0008111 |
| 3 *74:11 0.0751071 |
| 4 *74:10 0.0704457 |
| 5 *74:8 0.00648069 |
| 6 *74:7 0.00729179 |
| 7 *50:8 *74:8 0.0378845 |
| *RES |
| 1 *419:io_oeb[7] *74:7 10.305 |
| 2 *74:7 *74:8 96.75 |
| 3 *74:8 *74:10 4.5 |
| 4 *74:10 *74:11 548.46 |
| 5 *74:11 io_oeb[7] 37.125 |
| *END |
| |
| *D_NET *75 0.131831 |
| *CONN |
| *P io_oeb[8] O |
| *I *419:io_oeb[8] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[8] 0.000275016 |
| 2 *419:io_oeb[8] 0.000769355 |
| 3 *75:17 0.0521837 |
| 4 *75:16 0.0549893 |
| 5 *75:11 0.00630025 |
| 6 *75:10 0.00398894 |
| 7 *75:11 *78:8 0.00450255 |
| 8 *45:8 *75:11 0.00882207 |
| *RES |
| 1 *419:io_oeb[8] *75:10 13.275 |
| 2 *75:10 *75:11 46.53 |
| 3 *75:11 *75:16 31.77 |
| 4 *75:16 *75:17 405.27 |
| 5 *75:17 io_oeb[8] 3.015 |
| *END |
| |
| *D_NET *76 0.119465 |
| *CONN |
| *P io_oeb[9] O |
| *I *419:io_oeb[9] O *D wrapped_vga_clock |
| *CAP |
| 1 io_oeb[9] 0.000145669 |
| 2 *419:io_oeb[9] 0.00466995 |
| 3 *76:16 0.0550576 |
| 4 *76:15 0.0549119 |
| 5 *76:13 0.00466995 |
| 6 *48:11 *76:13 1.0415e-05 |
| *RES |
| 1 *419:io_oeb[9] *76:13 49.32 |
| 2 *76:13 *76:15 4.5 |
| 3 *76:15 *76:16 429.21 |
| 4 *76:16 io_oeb[9] 1.935 |
| *END |
| |
| *D_NET *77 0.261456 |
| *CONN |
| *P io_out[0] O |
| *I *419:io_out[0] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[0] 0.00462267 |
| 2 *419:io_out[0] 0.000174631 |
| 3 *77:16 0.0398872 |
| 4 *77:15 0.0352645 |
| 5 *77:13 0.0727951 |
| 6 *77:12 0.0727951 |
| 7 *77:10 0.0178712 |
| 8 *77:9 0.0180459 |
| *RES |
| 1 *419:io_out[0] *77:9 10.44 |
| 2 *77:9 *77:10 137.61 |
| 3 *77:10 *77:12 4.5 |
| 4 *77:12 *77:13 558.99 |
| 5 *77:13 *77:15 4.5 |
| 6 *77:15 *77:16 276.84 |
| 7 *77:16 io_out[0] 36.945 |
| *END |
| |
| *D_NET *78 0.191769 |
| *CONN |
| *P io_out[10] O |
| *I *419:io_out[10] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[10] 0.00421438 |
| 2 *419:io_out[10] 0.000697056 |
| 3 *78:14 0.0499108 |
| 4 *78:13 0.0456964 |
| 5 *78:11 0.0172005 |
| 6 *78:10 0.0172005 |
| 7 *78:8 0.00163787 |
| 8 *78:7 0.00233493 |
| 9 io_out[10] *112:21 0.000923493 |
| 10 *78:8 *84:8 0.00208049 |
| 11 *78:8 *86:8 0.0032608 |
| 12 *78:14 *112:21 0 |
| 13 *45:8 *78:8 0.0210228 |
| 14 *47:8 *78:8 0.0210863 |
| 15 *75:11 *78:8 0.00450255 |
| *RES |
| 1 *419:io_out[10] *78:7 8.865 |
| 2 *78:7 *78:8 87.93 |
| 3 *78:8 *78:10 4.5 |
| 4 *78:10 *78:11 130.41 |
| 5 *78:11 *78:13 4.5 |
| 6 *78:13 *78:14 357.84 |
| 7 *78:14 io_out[10] 36.945 |
| *END |
| |
| *D_NET *79 0.187101 |
| *CONN |
| *P io_out[11] O |
| *I *419:io_out[11] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[11] 0.000253458 |
| 2 *419:io_out[11] 0.00292241 |
| 3 *79:17 0.0743854 |
| 4 *79:16 0.0741319 |
| 5 *79:14 0.00802925 |
| 6 *79:13 0.00836969 |
| 7 *79:10 0.00326285 |
| 8 *79:10 *81:8 0.013961 |
| 9 *79:14 *87:8 0 |
| 10 *21:9 *79:13 0.00169236 |
| 11 *69:5 *79:13 9.29335e-05 |
| *RES |
| 1 *419:io_out[11] *79:10 48.015 |
| 2 *79:10 *79:13 9.09 |
| 3 *79:13 *79:14 60.03 |
| 4 *79:14 *79:16 4.5 |
| 5 *79:16 *79:17 578.07 |
| 6 *79:17 io_out[11] 2.835 |
| *END |
| |
| *D_NET *80 0.176879 |
| *CONN |
| *P io_out[12] O |
| *I *419:io_out[12] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[12] 0.000155499 |
| 2 *419:io_out[12] 0.000174631 |
| 3 *80:16 0.0142334 |
| 4 *80:15 0.0140779 |
| 5 *80:13 0.0302627 |
| 6 *80:12 0.0302627 |
| 7 *80:10 0.0437686 |
| 8 *80:9 0.0439433 |
| *RES |
| 1 *419:io_out[12] *80:9 10.44 |
| 2 *80:9 *80:10 340.11 |
| 3 *80:10 *80:12 4.5 |
| 4 *80:12 *80:13 232.29 |
| 5 *80:13 *80:15 4.5 |
| 6 *80:15 *80:16 110.97 |
| 7 *80:16 io_out[12] 1.755 |
| *END |
| |
| *D_NET *81 0.24704 |
| *CONN |
| *P io_out[13] O |
| *I *419:io_out[13] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[13] 0.000345078 |
| 2 *419:io_out[13] 0.000453406 |
| 3 *81:17 0.0735742 |
| 4 *81:16 0.0732291 |
| 5 *81:14 0.0244629 |
| 6 *81:13 0.024593 |
| 7 *81:8 0.00209779 |
| 8 *81:7 0.00242101 |
| 9 *81:8 *82:8 0.0246388 |
| 10 *81:14 *91:16 0 |
| 11 *21:9 *81:13 0.00363516 |
| 12 *24:19 *81:13 0.00362864 |
| 13 *79:10 *81:8 0.013961 |
| *RES |
| 1 *419:io_out[13] *81:7 7.605 |
| 2 *81:7 *81:8 63.09 |
| 3 *81:8 *81:13 18.81 |
| 4 *81:13 *81:14 186.57 |
| 5 *81:14 *81:16 4.5 |
| 6 *81:16 *81:17 572.67 |
| 7 *81:17 io_out[13] 3.375 |
| *END |
| |
| *D_NET *82 0.272851 |
| *CONN |
| *P io_out[14] O |
| *I *419:io_out[14] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[14] 0.000188785 |
| 2 *419:io_out[14] 0.000380333 |
| 3 *82:11 0.0746207 |
| 4 *82:10 0.0744319 |
| 5 *82:8 0.0425277 |
| 6 *82:7 0.042908 |
| 7 *82:8 *88:13 0.00976387 |
| 8 *82:8 *88:14 0 |
| 9 *82:8 *114:10 0.0033912 |
| 10 *81:8 *82:8 0.0246388 |
| *RES |
| 1 *419:io_out[14] *82:7 7.425 |
| 2 *82:7 *82:8 375.93 |
| 3 *82:8 *82:10 4.5 |
| 4 *82:10 *82:11 582.21 |
| 5 *82:11 io_out[14] 2.295 |
| *END |
| |
| *D_NET *83 0.186965 |
| *CONN |
| *P io_out[15] O |
| *I *419:io_out[15] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[15] 0.00107486 |
| 2 *419:io_out[15] 0.000304304 |
| 3 *83:16 0.00990123 |
| 4 *83:15 0.00882637 |
| 5 *83:13 0.0409764 |
| 6 *83:12 0.0409764 |
| 7 *83:10 0.0423006 |
| 8 *83:9 0.0426049 |
| *RES |
| 1 *419:io_out[15] *83:9 11.52 |
| 2 *83:9 *83:10 329.31 |
| 3 *83:10 *83:12 4.5 |
| 4 *83:12 *83:13 314.55 |
| 5 *83:13 *83:15 4.5 |
| 6 *83:15 *83:16 68.67 |
| 7 *83:16 io_out[15] 12.825 |
| *END |
| |
| *D_NET *84 0.289171 |
| *CONN |
| *P io_out[16] O |
| *I *419:io_out[16] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[16] 0.000201854 |
| 2 *419:io_out[16] 0.000586621 |
| 3 *84:11 0.0546446 |
| 4 *84:10 0.0544427 |
| 5 *84:8 0.0162291 |
| 6 *84:7 0.0168157 |
| 7 *84:7 *113:13 2.35229e-05 |
| 8 *84:8 *86:8 0.0200477 |
| 9 *84:8 *113:14 0.122815 |
| 10 *10:14 *84:8 0 |
| 11 *47:8 *84:8 0.00128375 |
| 12 *78:8 *84:8 0.00208049 |
| *RES |
| 1 *419:io_out[16] *84:7 8.325 |
| 2 *84:7 *84:8 308.61 |
| 3 *84:8 *84:10 4.5 |
| 4 *84:10 *84:11 417.51 |
| 5 *84:11 io_out[16] 2.295 |
| *END |
| |
| *D_NET *85 0.134407 |
| *CONN |
| *P io_out[17] O |
| *I *419:io_out[17] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[17] 0.00479225 |
| 2 *419:io_out[17] 0.000434913 |
| 3 *85:19 0.0365964 |
| 4 *85:18 0.0318042 |
| 5 *85:16 0.0157387 |
| 6 *85:15 0.0202793 |
| 7 *85:10 0.0141308 |
| 8 *85:9 0.0100251 |
| 9 *85:16 *111:11 0.000605426 |
| *RES |
| 1 *419:io_out[17] *85:9 12.06 |
| 2 *85:9 *85:10 59.31 |
| 3 *85:10 *85:15 42.75 |
| 4 *85:15 *85:16 125.73 |
| 5 *85:16 *85:18 4.5 |
| 6 *85:18 *85:19 244.44 |
| 7 *85:19 io_out[17] 36.945 |
| *END |
| |
| *D_NET *86 0.198029 |
| *CONN |
| *P io_out[18] O |
| *I *419:io_out[18] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[18] 0.00105188 |
| 2 *419:io_out[18] 0.00063513 |
| 3 *86:14 0.00428537 |
| 4 *86:13 0.00323349 |
| 5 *86:11 0.0536078 |
| 6 *86:10 0.0536078 |
| 7 *86:8 0.00147284 |
| 8 *86:7 0.00210797 |
| 9 *86:8 *90:8 0.00315948 |
| 10 *10:8 *86:14 0.0175012 |
| 11 *45:8 *86:8 0.00165215 |
| 12 *47:8 *86:8 0.0183187 |
| 13 *53:8 *86:8 0.0140862 |
| 14 *78:8 *86:8 0.0032608 |
| 15 *84:8 *86:8 0.0200477 |
| *RES |
| 1 *419:io_out[18] *86:7 8.505 |
| 2 *86:7 *86:8 94.95 |
| 3 *86:8 *86:10 4.5 |
| 4 *86:10 *86:11 409.59 |
| 5 *86:11 *86:13 4.5 |
| 6 *86:13 *86:14 46.53 |
| 7 *86:14 io_out[18] 12.645 |
| *END |
| |
| *D_NET *87 0.15598 |
| *CONN |
| *P io_out[19] O |
| *I *419:io_out[19] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[19] 0.00107486 |
| 2 *419:io_out[19] 6.13684e-05 |
| 3 *87:11 0.0135335 |
| 4 *87:10 0.0124586 |
| 5 *87:8 0.0427186 |
| 6 *87:7 0.04278 |
| 7 io_oeb[19] *87:11 0.00155819 |
| 8 *8:19 *87:8 0.000913148 |
| 9 *11:19 *87:8 0.0408818 |
| 10 *13:10 *87:11 0 |
| 11 *79:14 *87:8 0 |
| *RES |
| 1 *419:io_out[19] *87:7 4.905 |
| 2 *87:7 *87:8 379.89 |
| 3 *87:8 *87:10 4.5 |
| 4 *87:10 *87:11 101.07 |
| 5 *87:11 io_out[19] 12.825 |
| *END |
| |
| *D_NET *88 0.289353 |
| *CONN |
| *P io_out[1] O |
| *I *419:io_out[1] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[1] 0.000253458 |
| 2 *419:io_out[1] 0.00165605 |
| 3 *88:17 0.0743141 |
| 4 *88:16 0.0740606 |
| 5 *88:14 0.0614341 |
| 6 *88:13 0.0630902 |
| 7 *88:13 *114:10 0.0043497 |
| 8 *88:14 *114:10 0 |
| 9 *8:19 *88:14 0.00014428 |
| 10 *11:19 *88:14 0.000286996 |
| 11 *82:8 *88:13 0.00976387 |
| 12 *82:8 *88:14 0 |
| *RES |
| 1 *419:io_out[1] *88:13 43.245 |
| 2 *88:13 *88:14 472.41 |
| 3 *88:14 *88:16 4.5 |
| 4 *88:16 *88:17 580.77 |
| 5 *88:17 io_out[1] 2.835 |
| *END |
| |
| *D_NET *89 0.142275 |
| *CONN |
| *P io_out[20] O |
| *I *419:io_out[20] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[20] 0.0457642 |
| 2 *419:io_out[20] 0.000693084 |
| 3 *89:10 0.0464573 |
| 4 *4:14 io_out[20] 0.0255963 |
| 5 *50:8 io_out[20] 0.0237644 |
| 6 *60:14 *89:10 0 |
| *RES |
| 1 *419:io_out[20] *89:10 14.175 |
| 2 *89:10 io_out[20] 412.965 |
| *END |
| |
| *D_NET *90 0.205459 |
| *CONN |
| *P io_out[21] O |
| *I *419:io_out[21] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[21] 0.00132995 |
| 2 *419:io_out[21] 0.000697056 |
| 3 *90:14 0.00630202 |
| 4 *90:13 0.00497207 |
| 5 *90:11 0.0536475 |
| 6 *90:10 0.0536475 |
| 7 *90:8 0.00380937 |
| 8 *90:7 0.00450642 |
| 9 *90:8 *96:8 0.0074035 |
| 10 *45:8 *90:8 0.00344471 |
| 11 *53:8 *90:8 0.00686625 |
| 12 *54:8 *90:8 0.0202342 |
| 13 *54:14 *90:14 0.0300889 |
| 14 *58:8 *90:8 0.000563374 |
| 15 *59:8 *90:8 0.00478645 |
| 16 *86:8 *90:8 0.00315948 |
| *RES |
| 1 *419:io_out[21] *90:7 8.865 |
| 2 *90:7 *90:8 119.43 |
| 3 *90:8 *90:10 4.5 |
| 4 *90:10 *90:11 409.95 |
| 5 *90:11 *90:13 4.5 |
| 6 *90:13 *90:14 75.33 |
| 7 *90:14 io_out[21] 12.645 |
| *END |
| |
| *D_NET *91 0.143849 |
| *CONN |
| *P io_out[22] O |
| *I *419:io_out[22] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[22] 0.00478885 |
| 2 *419:io_out[22] 0.00263658 |
| 3 *91:20 0.0362289 |
| 4 *91:19 0.0314401 |
| 5 *91:17 0.018631 |
| 6 *91:16 0.0212676 |
| 7 *91:16 *97:11 0.00349425 |
| 8 *52:11 *91:17 0.0253622 |
| 9 *54:11 *91:16 0 |
| 10 *81:14 *91:16 0 |
| *RES |
| 1 *419:io_out[22] *91:16 49.68 |
| 2 *91:16 *91:17 207.99 |
| 3 *91:17 *91:19 4.5 |
| 4 *91:19 *91:20 241.74 |
| 5 *91:20 io_out[22] 36.945 |
| *END |
| |
| *D_NET *92 0.279643 |
| *CONN |
| *P io_out[23] O |
| *I *419:io_out[23] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[23] 0.000270799 |
| 2 *419:io_out[23] 0.00165133 |
| 3 *92:14 0.0360585 |
| 4 *92:13 0.0357877 |
| 5 *92:11 0.0305507 |
| 6 *92:10 0.032202 |
| 7 *92:11 *93:11 0.141455 |
| 8 *9:14 *92:11 0.00166699 |
| *RES |
| 1 *419:io_out[23] *92:10 24.3 |
| 2 *92:10 *92:11 375.03 |
| 3 *92:11 *92:13 4.5 |
| 4 *92:13 *92:14 275.49 |
| 5 *92:14 io_out[23] 2.835 |
| *END |
| |
| *D_NET *93 0.299013 |
| *CONN |
| *P io_out[24] O |
| *I *419:io_out[24] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[24] 0.00117627 |
| 2 *419:io_out[24] 0.00161237 |
| 3 *93:14 0.0323143 |
| 4 *93:13 0.0311381 |
| 5 *93:11 0.0416371 |
| 6 *93:10 0.0432495 |
| 7 *9:14 *93:11 0.00643036 |
| 8 *92:11 *93:11 0.141455 |
| *RES |
| 1 *419:io_out[24] *93:10 24.12 |
| 2 *93:10 *93:11 456.93 |
| 3 *93:11 *93:13 4.5 |
| 4 *93:13 *93:14 239.31 |
| 5 *93:14 io_out[24] 13.365 |
| *END |
| |
| *D_NET *94 0.175885 |
| *CONN |
| *P io_out[25] O |
| *I *419:io_out[25] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[25] 0.000323383 |
| 2 *419:io_out[25] 0.00308503 |
| 3 *94:11 0.0457281 |
| 4 *94:10 0.0454047 |
| 5 *94:8 0.0391294 |
| 6 *94:7 0.0422144 |
| *RES |
| 1 *419:io_out[25] *94:7 27.585 |
| 2 *94:7 *94:8 298.71 |
| 3 *94:8 *94:10 4.5 |
| 4 *94:10 *94:11 354.51 |
| 5 *94:11 io_out[25] 3.015 |
| *END |
| |
| *D_NET *95 0.186789 |
| *CONN |
| *P io_out[26] O |
| *I *419:io_out[26] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[26] 0.000242542 |
| 2 *419:io_out[26] 0.000311436 |
| 3 *95:14 0.022132 |
| 4 *95:13 0.0218895 |
| 5 *95:11 0.0314927 |
| 6 *95:10 0.0314927 |
| 7 *95:8 0.00979749 |
| 8 *95:7 0.0101089 |
| 9 *22:19 *95:8 0.0155234 |
| 10 *53:14 *95:8 0.0270321 |
| 11 *60:14 *95:8 0.0167662 |
| *RES |
| 1 *419:io_out[26] *95:7 6.345 |
| 2 *95:7 *95:8 227.97 |
| 3 *95:8 *95:10 4.5 |
| 4 *95:10 *95:11 241.29 |
| 5 *95:11 *95:13 4.5 |
| 6 *95:13 *95:14 170.91 |
| 7 *95:14 io_out[26] 2.475 |
| *END |
| |
| *D_NET *96 0.243504 |
| *CONN |
| *P io_out[27] O |
| *I *419:io_out[27] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[27] 0.00482637 |
| 2 *419:io_out[27] 0.000715963 |
| 3 *96:11 0.0278181 |
| 4 *96:10 0.0229918 |
| 5 *96:8 0.0204963 |
| 6 *96:7 0.0212123 |
| 7 *58:8 *96:8 0.13804 |
| 8 *90:8 *96:8 0.0074035 |
| *RES |
| 1 *419:io_out[27] *96:7 8.505 |
| 2 *96:7 *96:8 345.69 |
| 3 *96:8 *96:10 4.5 |
| 4 *96:10 *96:11 175.95 |
| 5 *96:11 io_out[27] 42.345 |
| *END |
| |
| *D_NET *97 0.150324 |
| *CONN |
| *P io_out[28] O |
| *I *419:io_out[28] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[28] 9.16379e-05 |
| 2 *419:io_out[28] 0.00084819 |
| 3 *97:17 0.0164111 |
| 4 *97:16 0.0200469 |
| 5 *97:11 0.0309487 |
| 6 *97:10 0.0280694 |
| 7 *97:11 *100:11 0.0154948 |
| 8 *97:11 *111:11 0.00268764 |
| 9 *97:11 *112:13 0.0101638 |
| 10 *97:11 *112:15 0.00914247 |
| 11 *419:io_in[27] *97:11 0 |
| 12 *39:13 *97:11 0.00169771 |
| 13 *62:5 *97:17 0.0112277 |
| 14 *91:16 *97:11 0.00349425 |
| *RES |
| 1 *419:io_out[28] *97:10 18.36 |
| 2 *97:10 *97:11 317.61 |
| 3 *97:11 *97:16 36.81 |
| 4 *97:16 *97:17 165.51 |
| 5 *97:17 io_out[28] 1.215 |
| *END |
| |
| *D_NET *98 0.204366 |
| *CONN |
| *P io_out[29] O |
| *I *419:io_out[29] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[29] 0.00179421 |
| 2 *419:io_out[29] 0.000270277 |
| 3 *98:15 0.0333515 |
| 4 *98:14 0.0315573 |
| 5 *98:12 0.0121263 |
| 6 *98:11 0.0121263 |
| 7 *98:9 0.0134442 |
| 8 *98:8 0.0137145 |
| 9 *7:8 *98:9 0.000839793 |
| 10 *21:9 *98:9 0.00120003 |
| 11 *24:19 *98:9 0.0656846 |
| 12 *32:11 *98:9 0.0150195 |
| 13 *35:19 *98:9 0.00323799 |
| *RES |
| 1 *419:io_out[29] *98:8 14.85 |
| 2 *98:8 *98:9 196.11 |
| 3 *98:9 *98:11 4.5 |
| 4 *98:11 *98:12 92.07 |
| 5 *98:12 *98:14 4.5 |
| 6 *98:14 *98:15 247.14 |
| 7 *98:15 io_out[29] 13.185 |
| *END |
| |
| *D_NET *99 0.232955 |
| *CONN |
| *P io_out[2] O |
| *I *419:io_out[2] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[2] 0.000124112 |
| 2 *419:io_out[2] 0.00147429 |
| 3 *99:14 0.0658939 |
| 4 *99:13 0.0657697 |
| 5 *99:11 0.0491096 |
| 6 *99:10 0.0505839 |
| 7 *99:10 *314:16 0 |
| 8 *59:8 *99:10 0 |
| *RES |
| 1 *419:io_out[2] *99:10 17.415 |
| 2 *99:10 *99:11 378.09 |
| 3 *99:11 *99:13 4.5 |
| 4 *99:13 *99:14 515.97 |
| 5 *99:14 io_out[2] 1.755 |
| *END |
| |
| *D_NET *100 0.186992 |
| *CONN |
| *P io_out[30] O |
| *I *419:io_out[30] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[30] 0.00429658 |
| 2 *419:io_out[30] 0.000653398 |
| 3 *100:14 0.0258396 |
| 4 *100:13 0.021543 |
| 5 *100:11 0.0464471 |
| 6 *100:10 0.0471005 |
| 7 *100:11 *110:11 0.00865489 |
| 8 *100:11 *111:11 0.0169625 |
| 9 *7:8 *100:11 0 |
| 10 *11:16 *100:11 0 |
| 11 *97:11 *100:11 0.0154948 |
| *RES |
| 1 *419:io_out[30] *100:10 17.46 |
| 2 *100:10 *100:11 465.57 |
| 3 *100:11 *100:13 4.5 |
| 4 *100:13 *100:14 164.79 |
| 5 *100:14 io_out[30] 38.025 |
| *END |
| |
| *D_NET *101 0.167863 |
| *CONN |
| *P io_out[31] O |
| *I *419:io_out[31] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[31] 0.000242542 |
| 2 *419:io_out[31] 0.00224411 |
| 3 *101:20 0.0651817 |
| 4 *101:19 0.0649391 |
| 5 *101:17 0.0132274 |
| 6 *101:16 0.0154715 |
| 7 *101:16 *114:11 0.000306883 |
| 8 *101:17 *107:11 0 |
| 9 *419:io_in[20] *101:16 0.00509955 |
| 10 *60:14 *101:16 0.000322893 |
| 11 *68:11 *101:16 0.000826953 |
| *RES |
| 1 *419:io_out[31] *101:16 49.32 |
| 2 *101:16 *101:17 100.17 |
| 3 *101:17 *101:19 4.5 |
| 4 *101:19 *101:20 505.71 |
| 5 *101:20 io_out[31] 2.475 |
| *END |
| |
| *D_NET *102 0.174701 |
| *CONN |
| *P io_out[32] O |
| *I *419:io_out[32] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[32] 0.000177869 |
| 2 *419:io_out[32] 0.020742 |
| 3 *102:11 0.0223864 |
| 4 *102:10 0.0222086 |
| 5 *102:8 0.0379665 |
| 6 *102:7 0.0379665 |
| 7 *102:5 0.020742 |
| 8 *15:12 *102:5 0.0125111 |
| *RES |
| 1 *419:io_out[32] *102:5 203.985 |
| 2 *102:5 *102:7 4.5 |
| 3 *102:7 *102:8 291.15 |
| 4 *102:8 *102:10 4.5 |
| 5 *102:10 *102:11 173.61 |
| 6 *102:11 io_out[32] 1.935 |
| *END |
| |
| *D_NET *103 0.170047 |
| *CONN |
| *P io_out[33] O |
| *I *419:io_out[33] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[33] 0.000113196 |
| 2 *419:io_out[33] 0.0259879 |
| 3 *103:11 0.0226189 |
| 4 *103:10 0.0225057 |
| 5 *103:8 0.0364167 |
| 6 *103:7 0.0364167 |
| 7 *103:5 0.0259879 |
| *RES |
| 1 *419:io_out[33] *103:5 201.285 |
| 2 *103:5 *103:7 4.5 |
| 3 *103:7 *103:8 279.81 |
| 4 *103:8 *103:10 4.5 |
| 5 *103:10 *103:11 176.31 |
| 6 *103:11 io_out[33] 1.395 |
| *END |
| |
| *D_NET *104 0.182386 |
| *CONN |
| *P io_out[34] O |
| *I *419:io_out[34] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[34] 0.00177706 |
| 2 *419:io_out[34] 0.000166616 |
| 3 *104:16 0.0418404 |
| 4 *104:15 0.0433895 |
| 5 *104:10 0.0129109 |
| 6 *104:9 0.00958484 |
| 7 *104:7 0.0362751 |
| 8 *104:5 0.0364417 |
| *RES |
| 1 *419:io_out[34] *104:5 1.305 |
| 2 *104:5 *104:7 277.83 |
| 3 *104:7 *104:9 4.5 |
| 4 *104:9 *104:10 74.43 |
| 5 *104:10 *104:15 34.65 |
| 6 *104:15 *104:16 314.64 |
| 7 *104:16 io_out[34] 13.185 |
| *END |
| |
| *D_NET *105 0.206057 |
| *CONN |
| *P io_out[35] O |
| *I *419:io_out[35] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[35] 0.000323383 |
| 2 *419:io_out[35] 9.76714e-05 |
| 3 *105:16 0.04218 |
| 4 *105:15 0.0451303 |
| 5 *105:10 0.0152824 |
| 6 *105:9 0.0120086 |
| 7 *105:7 0.045352 |
| 8 *105:5 0.0454497 |
| 9 *29:18 *105:15 0.000233283 |
| *RES |
| 1 *419:io_out[35] *105:5 0.765 |
| 2 *105:5 *105:7 348.03 |
| 3 *105:7 *105:9 4.5 |
| 4 *105:9 *105:10 92.97 |
| 5 *105:10 *105:15 34.65 |
| 6 *105:15 *105:16 327.87 |
| 7 *105:16 io_out[35] 3.015 |
| *END |
| |
| *D_NET *106 0.242408 |
| *CONN |
| *P io_out[36] O |
| *I *419:io_out[36] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[36] 0.00029243 |
| 2 *419:io_out[36] 0.0052125 |
| 3 *106:11 0.0536593 |
| 4 *106:10 0.0533669 |
| 5 *106:8 0.0623323 |
| 6 *106:7 0.0675448 |
| *RES |
| 1 *419:io_out[36] *106:7 43.785 |
| 2 *106:7 *106:8 479.61 |
| 3 *106:8 *106:10 4.5 |
| 4 *106:10 *106:11 338.31 |
| 5 *106:11 io_out[36] 2.475 |
| *END |
| |
| *D_NET *107 0.332064 |
| *CONN |
| *P io_out[37] O |
| *I *419:io_out[37] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[37] 0.000220124 |
| 2 *419:io_out[37] 0.000276453 |
| 3 *107:14 0.0801982 |
| 4 *107:13 0.0799781 |
| 5 *107:11 0.0721268 |
| 6 *107:10 0.0724033 |
| 7 *107:11 *314:19 0.0268614 |
| 8 *17:16 *107:11 0 |
| 9 *101:17 *107:11 0 |
| *RES |
| 1 *419:io_out[37] *107:10 15.66 |
| 2 *107:10 *107:11 587.07 |
| 3 *107:11 *107:13 4.5 |
| 4 *107:13 *107:14 507.15 |
| 5 *107:14 io_out[37] 1.935 |
| *END |
| |
| *D_NET *108 0.214717 |
| *CONN |
| *P io_out[3] O |
| *I *419:io_out[3] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[3] 0.000345078 |
| 2 *419:io_out[3] 0.00120729 |
| 3 *108:14 0.0651167 |
| 4 *108:13 0.0647716 |
| 5 *108:11 0.0410346 |
| 6 *108:10 0.0422419 |
| 7 *108:10 *314:16 0 |
| *RES |
| 1 *419:io_out[3] *108:10 16.875 |
| 2 *108:10 *108:11 315.99 |
| 3 *108:11 *108:13 4.5 |
| 4 *108:13 *108:14 507.87 |
| 5 *108:14 io_out[3] 3.375 |
| *END |
| |
| *D_NET *109 0.233623 |
| *CONN |
| *P io_out[4] O |
| *I *419:io_out[4] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[4] 0.000188785 |
| 2 *419:io_out[4] 0.000530865 |
| 3 *109:11 0.0747025 |
| 4 *109:10 0.0745137 |
| 5 *109:8 0.0354927 |
| 6 *109:7 0.0360236 |
| 7 *109:8 *114:10 0.0121705 |
| *RES |
| 1 *419:io_out[4] *109:7 7.965 |
| 2 *109:7 *109:8 287.19 |
| 3 *109:8 *109:10 4.5 |
| 4 *109:10 *109:11 582.75 |
| 5 *109:11 io_out[4] 2.295 |
| *END |
| |
| *D_NET *110 0.249962 |
| *CONN |
| *P io_out[5] O |
| *I *419:io_out[5] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[5] 0.00462267 |
| 2 *419:io_out[5] 0.000692357 |
| 3 *110:17 0.0492461 |
| 4 *110:16 0.0446234 |
| 5 *110:14 0.0424165 |
| 6 *110:13 0.0424165 |
| 7 *110:11 0.00330728 |
| 8 *110:10 0.00399963 |
| 9 *110:11 *111:11 0.0382393 |
| 10 *7:8 *110:11 0 |
| 11 *11:16 *110:11 0 |
| 12 *61:11 *110:11 0.0117437 |
| 13 *100:11 *110:11 0.00865489 |
| *RES |
| 1 *419:io_out[5] *110:10 17.64 |
| 2 *110:10 *110:11 96.03 |
| 3 *110:11 *110:13 4.5 |
| 4 *110:13 *110:14 324.27 |
| 5 *110:14 *110:16 4.5 |
| 6 *110:16 *110:17 349.74 |
| 7 *110:17 io_out[5] 36.945 |
| *END |
| |
| *D_NET *111 0.276565 |
| *CONN |
| *P io_out[6] O |
| *I *419:io_out[6] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[6] 0.000253458 |
| 2 *419:io_out[6] 0.000695968 |
| 3 *111:17 0.0491492 |
| 4 *111:16 0.0488958 |
| 5 *111:14 0.0343588 |
| 6 *111:13 0.0343588 |
| 7 *111:11 0.00499265 |
| 8 *111:10 0.00568862 |
| 9 *111:11 *112:13 0.00359577 |
| 10 *111:11 *112:15 0.0307745 |
| 11 *7:8 *111:11 0 |
| 12 *39:13 *111:11 0.00295238 |
| 13 *56:13 *111:11 0.00235462 |
| 14 *85:16 *111:11 0.000605426 |
| 15 *97:11 *111:11 0.00268764 |
| 16 *100:11 *111:11 0.0169625 |
| 17 *110:11 *111:11 0.0382393 |
| *RES |
| 1 *419:io_out[6] *111:10 17.82 |
| 2 *111:10 *111:11 191.61 |
| 3 *111:11 *111:13 4.5 |
| 4 *111:13 *111:14 262.35 |
| 5 *111:14 *111:16 4.5 |
| 6 *111:16 *111:17 383.67 |
| 7 *111:17 io_out[6] 2.835 |
| *END |
| |
| *D_NET *112 0.245955 |
| *CONN |
| *P io_out[7] O |
| *I *419:io_out[7] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[7] 0.00127974 |
| 2 *419:io_out[7] 0.00098943 |
| 3 *112:24 0.0262663 |
| 4 *112:23 0.0249865 |
| 5 *112:21 0.0544883 |
| 6 *112:20 0.0552996 |
| 7 *112:15 0.00146433 |
| 8 *112:13 0.00164248 |
| 9 io_out[10] *112:21 0.000923493 |
| 10 *35:19 *112:21 0 |
| 11 *38:19 *112:21 0 |
| 12 *39:13 *112:15 0.0108371 |
| 13 *56:13 *112:13 0.00234692 |
| 14 *57:11 *112:20 8.2093e-05 |
| 15 *70:5 *112:21 0.0116721 |
| 16 *78:14 *112:21 0 |
| 17 *97:11 *112:13 0.0101638 |
| 18 *97:11 *112:15 0.00914247 |
| 19 *111:11 *112:13 0.00359577 |
| 20 *111:11 *112:15 0.0307745 |
| *RES |
| 1 *419:io_out[7] *112:13 44.01 |
| 2 *112:13 *112:15 77.4 |
| 3 *112:15 *112:20 13.77 |
| 4 *112:20 *112:21 442.53 |
| 5 *112:21 *112:23 4.5 |
| 6 *112:23 *112:24 191.97 |
| 7 *112:24 io_out[7] 12.825 |
| *END |
| |
| *D_NET *113 0.225376 |
| *CONN |
| *P io_out[8] O |
| *I *419:io_out[8] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[8] 0.000345078 |
| 2 *419:io_out[8] 0.00111355 |
| 3 *113:14 0.0413426 |
| 4 *113:13 0.0421111 |
| 5 *10:14 *113:14 0 |
| 6 *44:8 *113:14 0 |
| 7 *45:8 *113:13 0.00880485 |
| 8 *59:8 *113:13 0.00882026 |
| 9 *84:7 *113:13 2.35229e-05 |
| 10 *84:8 *113:14 0.122815 |
| *RES |
| 1 *419:io_out[8] *113:13 41.625 |
| 2 *113:13 *113:14 468.81 |
| 3 *113:14 io_out[8] 3.375 |
| *END |
| |
| *D_NET *114 0.271655 |
| *CONN |
| *P io_out[9] O |
| *I *419:io_out[9] O *D wrapped_vga_clock |
| *CAP |
| 1 io_out[9] 0.000188785 |
| 2 *419:io_out[9] 0.00138202 |
| 3 *114:17 0.0305142 |
| 4 *114:16 0.0303254 |
| 5 *114:14 0.00822 |
| 6 *114:13 0.00822 |
| 7 *114:11 0.0244167 |
| 8 *114:10 0.0257987 |
| 9 *22:19 *114:11 0.00367313 |
| 10 *42:8 *114:11 0.0645036 |
| 11 *44:8 *114:11 0.00130753 |
| 12 *47:14 *114:11 0 |
| 13 *60:14 *114:11 0.0528861 |
| 14 *82:8 *114:10 0.0033912 |
| 15 *88:13 *114:10 0.0043497 |
| 16 *88:14 *114:10 0 |
| 17 *101:16 *114:11 0.000306883 |
| 18 *109:8 *114:10 0.0121705 |
| *RES |
| 1 *419:io_out[9] *114:10 47.835 |
| 2 *114:10 *114:11 344.79 |
| 3 *114:11 *114:13 4.5 |
| 4 *114:13 *114:14 62.55 |
| 5 *114:14 *114:16 4.5 |
| 6 *114:16 *114:17 237.87 |
| 7 *114:17 io_out[9] 2.295 |
| *END |
| |
| *D_NET *313 0.284928 |
| *CONN |
| *P wb_clk_i I |
| *I *419:wb_clk_i I *D wrapped_vga_clock |
| *CAP |
| 1 wb_clk_i 0.000272504 |
| 2 *419:wb_clk_i 0.0572408 |
| 3 *313:15 0.0572408 |
| 4 *313:13 0.0849396 |
| 5 *313:11 0.0852121 |
| 6 *313:11 *314:13 2.18956e-05 |
| 7 *69:8 *313:13 0 |
| *RES |
| 1 wb_clk_i *313:11 2.655 |
| 2 *313:11 *313:13 652.95 |
| 3 *313:13 *313:15 4.5 |
| 4 *313:15 *419:wb_clk_i 361.845 |
| *END |
| |
| *D_NET *314 0.415662 |
| *CONN |
| *P wb_rst_i I |
| *I *419:wb_rst_i I *D wrapped_vga_clock |
| *CAP |
| 1 wb_rst_i 0.00034474 |
| 2 *419:wb_rst_i 0.000315182 |
| 3 *314:19 0.00338241 |
| 4 *314:18 0.00306723 |
| 5 *314:16 0.0389233 |
| 6 *314:15 0.0389233 |
| 7 *314:13 0.0696084 |
| 8 *314:11 0.0699531 |
| 9 *24:15 *314:16 0 |
| 10 *28:19 *314:16 0.153825 |
| 11 *60:13 *314:19 0.0104362 |
| 12 *99:10 *314:16 0 |
| 13 *107:11 *314:19 0.0268614 |
| 14 *108:10 *314:16 0 |
| 15 *313:11 *314:13 2.18956e-05 |
| *RES |
| 1 wb_rst_i *314:11 3.015 |
| 2 *314:11 *314:13 535.41 |
| 3 *314:13 *314:15 4.5 |
| 4 *314:15 *314:16 488.97 |
| 5 *314:16 *314:18 4.5 |
| 6 *314:18 *314:19 69.03 |
| 7 *314:19 *419:wb_rst_i 15.84 |
| *END |
